Advanced Micro Devices Corporation

Globalfoundries Inc.

Spansion Llc.

Advanced Micro Drvices, Inc.

Cyrus E Tabery

Bin Yu

Srikanteswara Dakshina-Murthy

Qi Xiang

Eric N Paton

Robert B Ogle

Chih-Yuh Yang

Richard J Huang

Christopher F Lyons

Philip A Fisher

Scott Allan Bell

Minh Van Ngo

Haihong Wang

Hung-Eil Kim

Bhanwar Singh

Todd P Lukanc

Shibly S Ahmed

Luigi Capodieci

Christopher A Spence

Carl P Babcock

Chris Haidinyak

Richard C Nguyen

Ramkumar Subramanian

Bharath Rangarajan

Hiroyuki Kinoshita

Judy Xilin An

Jeff P Erhardt

Zoran Krivokapic

Khoi A Phan

Ming-Ren Lin

Ning Cheng

Jean Y Yang

Bruno M LaFontaine

Mark T Ramsbey

Steven C Avanzino

Lu You

Jean Yee-Mei Yang

Jaeyong Park

Emmanuil Lingunis

Adam R Pawloski

Matthew S Buynoski

Yu Nan Sun

Jongwook Kye

Harry Jay Levinson

William George En

Tazrien Kamal

Krishnashree Achuthan

Ivan Lalovic

Gilles Amblard

Christopher Foster

John R Behnke

Clarence B Ferguson

Amr Yehia Abdo

Jeffrey A Schefske

Frank Tsai

Basab Banerjee

Mark W Randolph

Jeffrey Allan Shields

Arvind Halliyal

Hidehiko Shiraiwa

Marina V Plat

Dawn M Hopper

Joong Jeon

David E Brown

Weidong Qian

Anna Maria Minvielle

Patrick K Cheung

Tyagamohan Gottipati

Joerg Reiss

John Caffall

Ivan Lavolic

Srikanteswara Dakshina-Murhty

Minh-Ren Lin

A method of forming an integrated circuit includes providing a buffer layer comprising a dielectric material above a layer of conductive material and providing a layer of mask material above the buffer layer. The mask material comprises amorphous carbon. The method also includes removing a portion of the buffer layer and the layer of mask material to form a mask. A feature is formed in the layer of conductive material according to the mask.

Mask for forming integrated circuit

A double gate metal-oxide semiconductor field-effect transistor (MOSFET) includes a fin, a first gate and a second gate. The first gate is formed on top of the fin. The second gate surrounds the fin and the first gate. In another implementation, a triple gate MOSFET includes a fin, a first gate, a second gate, and a third gate. The first gate is formed on top of the fin. The second gate is formed adjacent the fin. The third gate is formed adjacent the fin and opposite the second gate.

Double and triple gate MOSFET devices and methods for making same

Methods are provided for forming contacts for a semiconductor device. The methods may include depositing various materials, such as polysilicon, nitride, oxide, and/or carbon materials, over the semiconductor device. The methods may also include forming a contact hole and filling the contact hole to form the contact for the semiconductor device.

Methods for forming small contacts

A method of fabricating a semiconductor device using lithography. The method can include providing a wafer assembly having a layer to be processed disposed under a photo resist layer and illuminating the wafer assembly with an exposure dose transmitted through a birefringent material disposed between a final optical element of an imaging subsystem used to transmit the exposure dose and the photo resist layer. Also disclosed is a wafer assembly from which at least one semiconductor device can be fabricated. The wafer assembly can include a layer to be processed, a photo resist layer disposed over the layer to be processed and a contrast enhancing, birefringent top anti-reflecting coating (TARC).

Wafer assembly having a contrast enhancing top anti-reflecting coating and method of lithographic processing

A process for fabricating a semiconductor device, including applying an immersion lithography medium to a surface of a semiconductor wafer; exposing a material on the surface of the semiconductor wafer to electromagnetic radiation having a selected wavelength; and applying supercritical carbon dioxide to the semiconductor wafer to remove the immersion lithography medium from the surface of the semiconductor wafer. In one embodiment, the process includes recovery of the immersion lithography medium.

Method for removal of immersion lithography medium in immersion lithography processes

A method of selecting a plurality of lithography process parameters for patterning a layout on a wafer includes simulating how the layout will print on the wafer for a plurality of resolution enhancement techniques (RETs), where each RET corresponds to a plurality of lithography process parameters. For each RET, the edges of structures within the simulated layout can be classified based on manufacturability. RETs that provide optimal manufacturability can be selected. In this manner, the simulation tool can be used to determine the optimal combination of scanner setup and reticle type for minimizing the variation in wafer critical dimension (CD).

System and method for integrated circuit device design and manufacture using optical rule checking to screen resolution enhancement techniques

A method includes providing an initial IC device design, which design has a desired set of electrical characteristics. A layout representation corresponding to the initial device design is generated. A simulation tool is used to determine whether the layout representation corresponds to an IC device design having the desired electrical characteristics. In addition, the variation between structures within IC device designed due to process variations is evaluated using the simulation tool. This variation can be used to determine whether the design is optimized.

System and method for designing an integrated circuit device

Method for forming integrated circuit

A semiconductor device may include a substrate and an insulating layer formed on the substrate. A fin may be formed on the insulating layer. The fin may include a side surface and a top surface, and the side surface may have a &#x3c;100&#x3e; orientation. A first gate may be formed on the insulating layer proximate to the side surface of the fin.

Formation of semiconductor devices to achieve &#x3c;100&#x3e; channel orientation

A method of forming a plurality of contact holes of varying pitch and density in a contact layer of an integrated circuit device is provided. The plurality of contact holes can include a plurality of regularly spaced contact holes having a first pitch along a first direction and a plurality of semi-isolated contact holes having a second pitch along a second direction. A double-dipole illumination source can transmit light energy through a mask having a pattern corresponding to a desired contact hole pattern. The double-dipole illumination source can include a first dipole aperture, which is oriented and optimized for patterning the regularly spaced contact holes, and a second dipole aperture, which is oriented substantially orthogonal to the first dipole aperture and optimized for patterning the plurality of semi-isolated contact holes. The contact layer can be etched using the patterned photoresist layer.

System and method for fabricating contact holes

A method of manufacturing a semiconductor device includes forming a gate electrode over a substrate, implanting dopants into the substrate and activating the dopants using laser thermal annealing. During annealing, the laser and substrate are moved relative to one another, and the movement of the laser and the substrate relative to one another does not pause between and during activating one portion of the source/drain regions and activating another portion of the source/drain regions. Each pulse from the laser can respectively irradiate different portions of the source/drain regions, and a spot area of the laser is less than 50 millimeter.

Scanning laser thermal annealing

A method of producing a layout representation corresponding to an integrated circuit (IC) device design can include generating an initial layout representation in accordance with a predetermined set of design rules and simulating how structures within the initial layout representation will pattern on a wafer. Based on the simulation, portions of the layout representation, which include structures demonstrating poor manufacturability and/or portions of the layout representation in which extra manufacturability margin is present, can be identified. Portions of the layout representation including structures demonstrating poor manufacturability and/or in which extra manufacturability margin is present can be modified to optimize the layout representation.

Optimizing an integrated circuit layout by taking into consideration layout interactions as well as extra manufacturability margin

A method of reflective lithography includes directing an asymmetric radiation (light) beam onto a reticle of a reflective lithography system. The asymmetry in the shape of the radiation beam may be used to compensate for a non-zero (non-normal) angle of incidence of the incident radiation. The radiation source shape may be configured to produce a substantially-symmetric output from the reticle. The shape of the radiation source may be configurable by any of a variety of suitable methods, for example by use of a configurable reflective device such as a fly's eye mirror, or by use of one or more suitable mirrors, lenses, and/or slits.

Lithography mask utilizing asymmetric light source

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Santa Clara, CA, United States of America

Cyrus E Tabery