Commissariat &#xc0; L'&#xc9;nergie Atomique Et Aux &#xc9;nergies Alternatives

Stmicroelectronics S.a.

Stmicroelectronics (crolles 2) Sas

Centre National De La Recherche Scientifique

Commissariat a L'energie Atomique

Centre Nationale De La Recherche Scientifique

Commissariat a L'energie Atomique Et Aux Energies Alternatives

Cyrille Le Royer

Fabrice Nemouchi

Nicolas Posseme

Yves Morand

Louis Hutin

Shay Reboh

Sorin Ioan Cristoloveanu

François Lefloch

Jing Wan

Alexander Zaslavsky

Maud Vinet

Laurent Grenouillet

Laurent Clavelier

Heimanu Niebojewski

Costin Anghel

Loic Gaben

Joël Kanyandekwe

Sébastien Kerdiles

Frédéric Boeuf

Sylvain Maitrejean

Sylvain Barraud

Adam Makosiej

Olivier Faynot

Jean-François Damlencourt

Loïc Gaben

A method for making a device with superconductor qubit(s) including at least one JoFET formed by the following steps of: and wherein the materials and the thicknesses of the protective dielectric portion and of the protective dielectric layer are selected so as to prevent the laser pulse from reaching the first region, and melting the semiconductor of the second regions which forms, after cooling, a recrystallised semiconductor material having superconductor material properties.

Method for making an electronic device with superconductor qubit(s) including at least one JoFET

A quantum device includes a transistor pattern carried by a substrate, the transistor pattern having, in a stack, a gate dielectric and a superconducting gate on the gate dielectric. The superconducting gate has a base, a tip, sidewalls and at least one superconducting region made of a material that has, as a main component, at least one superconducting element. The superconducting gate also includes a basal portion having a dimension, taken in a first direction of a basal plane that is smaller than a dimension of the tip of the superconducting gate. The transistor pattern further includes at least one dielectric portion made of a dielectric material in contact with the top face of the gate dielectric and the basal portion of the superconducting gate.

Quantum device and method for producing the same

A semiconductor device made on a substrate including an active region and a non-active region at least partially surrounding the active region, a plurality of gate stacks, a part of each gate stack being on the active region, each gate stack being separated from adjacent gate stacks by a spacer by a distance e, the device being such that, for each gate stack, the part of the gate stack located on the active region has a height h, the part of the same gate stack located on the non-active region has a height h, and h/e=aand h/e=a<awhere ais an aspect ratio such that, upon growth of the spacer material forming the spacers, an airgap is in the spacer, and ais an aspect ratio such that, upon growth of the spacer material forming the spacers, no airgap is in the spacer.

Device comprising spacers including a localised airgap and associated manufacturing methods

A method for manufacturing a pFET transistor, the method for manufacturing the transistor including providing a base structure comprising a silicon channel and a gate structure, the gate structure surrounding the channel leaving two flanks of the channel free; growing a first layer made from silicon-germanium alloy on the flanks of the channel; enriching the channel with germanium atoms from the first layer; and forming a drain region and a source region on either side of the channel.

Method for manufacturing a transistor with a gate-all-around structure

A method for producing a quantum device comprising providing a substrate having a front face and carrying at least one transistor pattern on the front face thereof, said transistor pattern comprising, in a stack a gate dielectric on the front face of the substrate, and a gate on the gate dielectric, said gate having a top and sidewalls. The method further includes forming a protective layer at the front face of the substrate, said protective layer being configured to prevent diffusion of at least one metal species in the substrate, forming a metal layer that has, as a main component, at least one metal species, at least on the sidewalls of the gate, said at least one metal species comprising at least one superconducting element, and forming a superconducting region in the gate by lateral diffusion of the at least one superconducting element from the sidewalls of said gate.

Method of making a quantum device

A method for forming SiGe-based regions with different Ge concentrations is provided. After defining the regionson a SOI substrate, a grating of masking patterns is formed on at least one region. After the epitaxial growth of a Ge-based layer in each of the regions, a first vertical diffusion is carried out. A second horizontal diffusion is then carried out such that the Ge diffuses beneath the masking patterns of the region. Thus, the regionhas a Ge concentration that is lower than the Ge concentration of the region

Method for producing SiGe-based zones at different concentrations of Ge

Method for producing a semiconductor device, including:

Method for producing at least one device in compressive strained semiconductor

A method is provided for producing a component based on a plurality of transistors on a substrate including an active area and an electrical isolation area, each transistor including a gate and spacers on either side of the gate, the electrical isolation area including at least one cavity formed as a hollow between a spacer of a first transistor of the plurality of transistors and a spacer of a second transistor of the plurality of transistors, the first and the second transistors being adjacent, the method including: forming the gates of the transistors; forming the spacers; and forming a mechanically constraining layer for the transistors; and after forming the spacers and before forming the mechanically constraining layer, forming a filling configured to at least partially fill, with a filling material, the at least one cavity within the electrical isolation area, between the spacers of the first and the second transistors.

Method for producing a component by filling a cavity within an electrical isolation area with carbon-based material

A process for fabricating an electronic component with multiple quantum dots is provided, including providing a stack including a substrate, a nanostructure made of semiconductor material superposed over the substrate and including first and second quantum dots and a link linking the quantum dots, first and second control gate stacks arranged on the quantum dots, the gate stacks separated by a gap, the quantum dots and the link having a same thickness; partially thinning the link while using the gate stacks as masks to obtain the link, a thickness of which is less than that of the quantum dots; and conformally forming a dielectric layer on either side of the gate stacks so as to fill the gap above the partially thinned link. An electronic component with multiple quantum dots is also provided.

Method for manufacturing an electronic component having multiple quantum dots

A process for fabricating an integrated circuit is provided, including steps of providing a substrate including a silicon layer, a layer of insulator a layer of hard mask and accesses to first and second regions of the silicon layer; forming first and second deposits of SiGe alloy on the first and the second regions in order to form first and second stacks; then protecting the first deposit and maintaining an access to the second deposit; then performing an etch in order to form trenches between the hard mask and two opposite edges of the second stack; then forming a tensilely strained silicon layer in the second region via amorphization of the second region; then crystallization; and enriching the first region in germanium by diffusion from the first deposit.

Method for fabricating an integrated circuit including a NMOS transistor and a PMOS transistor

There is provided a method for producing, on one same wafer, at least one first transistor surmounted at least partially on a voltage stressed layer and a second transistor surmounted at least partially on a compression stressed layer, the method including providing a wafer including the first and the second transistors; forming at least one stressed nitride-based layer, on the first and the second transistors, the layer being voltage stressed; depositing a protective layer so as to cover a first zone of the layer, the first zone covering at least partially the first transistor and leaving a second zone of the layer uncovered, the second zone at least partially covering the second transistor; and modifying a type of stress of the second zone of the layer by implanting hydrogen-based ions from a plasma in the second zone, such that the second zone of the layer is compression stressed.

Fabrication of transistors having stressed channels

A method is provided for producing a microelectronic component on a substrate including in an exposed manner on a first face thereof, an active zone and an electrical isolation zone adjacent thereto, the method including forming a gate on the active zone, forming spacers each configured to cover a surface of a different edge of the gate, and forming source and drain zones by doping portions of the active zone adjacent to the gate, the method successively including forming a first layer of spacer material above the active zone and the electrical isolation zone; an ion implantation to produce doping of the portions through the first layer; removing a modified portion of the first layer disposed overlooking the portions, the modified portion coming from the ion implantation, the removing being configured to preserve at least part of the first layer at a level of edges of the gate.

Method of producing microelectronic components

A method of fabrication, including the steps for supplying a substrate including a layer of semiconductor material covered by a sacrificial gate including a sacrificial gate insulator including a middle part, and edges covered by sacrificial spacers and having a thickness tox; removal of the sacrificial gate insulator and the sacrificial gate material; formation of a conformal deposition of thickness thk of dielectric material inside of the groove formed in order to form a gate insulator, with tox&#x3e;thk&#x2267;tox/2; formation of a gate electrode within the groove; removal of the sacrificial spacers so as to open up edges of the gate insulator layer; formation of spacers on the edges of the gate insulator layer on either side of the gate electrode, these spacers having a dielectric constant at the most equal to 3.5.

Method for fabrication of a field-effect with reduced stray capacitance

Method to strain a channel zone of a transistor of the semiconductor on insulator type transistor that makes use of an SMT stress memorization technique in which regions located under the insulation layer of the substrate (FIG.) are amorphized, before the transistor gate is made.

Local strain generation in an SOI substrate

A tunnel-effect transistor the drain region of which includes a first zone doped with a doping of a first type, and a second zone doped with a doping of a second type forming a junction with the first zone.

Growing community of inventors

Tullins-Fures, France

Cyrille Le Royer