Stmicroelectronics S.a.

Stmicroelectronics Gmbh

Cyrille Dray

Richard P Fournel

Sébastien Barasinski

Jean Lasseuguette

Christophe Frey

Daniel Caspar

Francois Jacquet

Sigrid Thomas

Philippe Candelier

Philippe Gendrier

Stéphane Gamet

Sébastien Poirier

Phillipe Gendrier

A device, and a corresponding method of implementation, for SRAM memory information storage are provided. The device is powered by a supply voltage and includes an array of base cells organized in base columns, and at least one mirror column of at least one mirror cell liable to simulate the behavior of the cells in a base column. The device further includes Emulation means, in a mirror column, of the most restricting cell in a base column, Means for varying a mirror power supply voltage for the mirror column, and Means for copying the mirror power supply voltage in the emulated base column.

Method for implementing an SRAM memory information storage device

A buffer circuit includes at least one part that is powered by a supply voltage by means of a first initialization transistor, and connected to the ground by means of a second initialization transistor. The circuit is capable of transferring, between an input and an output, an input signal including at least one rising edge and/or one falling edge. The circuit includes a first CMOS inverter, of which the input is connected to the input of the circuit, and of which the output is mounted in series with the input of a second CMOS inverter, with the output of the second CMOS inverter being connected to the output of the circuit. A circuit creates an overvoltage on one of the two inverters during operation.

High-speed buffer circuit, system and method

A device, and a corresponding method of implementation, for SRAM memory information storage are provided. The device is powered by a supply voltage and includes an array of base cells organized in base columns, and at least one mirror column of at least one mirror cell liable to simulate the behavior of the cells in a base column. The device further includes Emulation means, in a mirror column, of the most restricting cell in a base column, Means for varying a mirror power supply voltage (VDDMMOCK) for the mirror column, and Means for copying the mirror power supply voltage in the emulated base column.

SRAM memory device with improved write operation and method thereof

The invention relates to a device for setting up a write current on at least one write conducting line in an MRAM type integrated circuit memory, including a current mirror composed of a first stage acting as the reference regulated cascode stage receiving all or part of the write current on its input and a second stage acting as the copy regulated cascode stage copying the write current onto the write line.

Device for setting up a write current in an MRAM type memory and memory comprising

An embodiment of the invention pertains to an norder selector switch device comprising: a first arm comprising n transistors series-connected between a first input to which a 0-ranking potential is applied, and an output; and a second arm comprising n transistors series-connected between a second input to which a 0-ranking potential is applied, and the output. The device according to the invention also comprises: a means to produce n&#x2212;1 potentials ranked 1 to n&#x2212;1 included between the potential ranked 0 and the potential ranked n; and a driving means for the production, from the n+1 potentials ranked 0 to n, of control signals suited to driving the gates of the transistors of the first arm and the gates of the transistors of the second arm so that the transistors of one of the arms are on and the transistors of the other arm are off depending on the value of the n-ranking potential relative to the value of the 0-ranking potential.

Recursive device for switching over a high potential greater than a nominal potential of a technology in which the device is made and related system and method

A memory is organized with many memory subspaces (db&#x3c;i&#x3e;) each including their own read-out circuit (SA&#x3c;i&#x3e;). At least one redundant column (Blred) is provided within each subspace in order to compensate for at least one defective column of said subspace. A memory controller is provided for interacting with the memory via a write bus (TD) and a read bus (Q). The memory controller generates a signal (TD&#x3c;i&#x3e;) for enabling the redundant column. This signal is provided so as to be conveyed to the read-out circuits of the memory to which the write bus (TD) is connected. Thus, one enables, via the read-out circuits, the redundant column of the memory subspaces which are associated with a defective column address.

Column redundancy system for an integrated circuit memory

A random access memory array includes random access memory elements arranged in a rows and columns. The elements of each row have a word line and a write digit line and the elements of each column have a bit line and a write bit line. A first selection circuit/transistor for each row has a first source-drain path coupled in the write digit line and a gate terminal coupled to the word line. A second selection circuit/transistor for each column has a second source-drain path coupling in the write bit line and a gate terminal coupled to the bit line. A first write signal is applied to one word line to actuate the first selection circuit/transistor for the row corresponding to that one word line and cause a write current to flow through the first source-drain path of the actuated first selection circuit/transistor and the corresponding write digit line to write data into certain memory elements in that row. A second write signal is applied to one bit line to actuate the second selection circuit/transistor for the column corresponding to that one bit line and cause a write current to flow through the second source-drain path of the actuated second selection circuit/transistor and the corresponding write bit line to write data into at least one memory element in that column.

Magnetic random access memory array having bit/word lines for shared write select and read operations

The semiconductor memory device includes an electrically erasable programmable non-volatile memory cell having a single layer of gate material and including a floating-gate transistor and a control gate. The source, drain and channel regions of the floating-gate transistor form the control gate. Moreover, the memory cell includes a dielectric zone lying between a first part of the layer of gate material and a first semiconductor active zone electrically isolated from a second active zone incorporating the control gate. This dielectric zone then forms a tunnel zone for transferring, during erasure of the cell, the charges stored in the floating gate to the first active zone.

Electrically erasable and programmable, non-volatile semiconductor memory device having a single layer of gate material, and corresponding memory plane

A memory device includes at least one segmented writing line formed by at least one writing segment. A programming circuit is controlled by a line address circuit in a writing mode of the memory device to program at least one memory cell coupled to the segmented writing line. A reading bit line is connected to a reading circuit for reading the contents of the cell in a reading mode of the memory device. The reading bit line cooperates in writing mode with the line address circuit to control the programming circuit of the segmented writing line.

Memory architecture with segmented writing lines

A switch arrangement for switching a node between three supply voltages based on two control signals. The switch arrangement includes three circuits for connecting an output node with one of three nodes, each of which is set to a different voltage. The switch arrangement is controlled by six control signals that establish mutually exclusive switching modes and avoid combinational currents. The switch arrangement is also designed to allow the use of MOS transistors having a low nominal voltage, with a value that is lower than the highest voltage to be switched. The switch arrangement is particularly adapted to supply power to non-volatile memory cells.

Switch arrangement for switching a node between different voltages without generating combinational currents

The semiconducting memory device comprises a non-volatile programmable and electrically erasable memory cell with a single layer of grid material and comprising a floating grid transistor and a control grid, within an active semiconducting area formed in a region of the substrate and delimited by an isolation region. The layer of grid material EG, FL Pin which the floating grid FG is made extends integrall above the active area ZA without overlapping part of the isolation region STI, and the transistor is electrically isolated from the control grid CG by PN junctions that will be reverse biased.

Non-volatile programmable and electrically erasable memory with a single layer of gate material

Control device for a generation circuit (REF) for reference voltages (VPOL, VPOL), includes a first P type MOS transistor (M), connected between a node (N) to which a high voltage signal (EHV) is applied and a first intermediate node (A), a second P type MOS transistor (M) connected between the first intermediate node (A) and a second intermediate node (B), and a third P type MOS transistor (M) connected between the second node and the ground and with its grid connected to its drain, to supply a reference voltage (VPOL, VPOL) on one of the first and second intermediate nodes (A, B). The control device includes a controlling mechanism for controlling the reference transistors, either in a first or second operating mode.

Device for controlling a circuit generating reference voltages

The FAMOS memory location comprises a single floating gate (GR) overlapping an active surface of a semiconductor substrate according to at least two asymmetrical overlap profiles (PF , PF ) so as to define at least two electrodes in the active region. Memory location programming means (MC, SW) are capable of selectively applying different predetermined sets of bias voltages to the electrodes so as to confer at least three programming logic levels on the memory location.

Memory cell of the famos type having several programming logic levels

An FAMOS memory includes memory cells, with each memory cell including an insulated gate transistor, and a first access transistor having a drain connected to a source of the insulated gate transistor. The FAMOS memory also includes an insulation transistor having a drain and a source respectively connected to the source of the insulated gate transistors of two adjacent cells of a same row. Each insulated gate transistor has a ring structure, and a ladder-shaped separation region insulates the cells of the same row.

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Grenoble, France

Cyrille Dray