International Business Machines Corporation

Globalfoundries Inc.

Ultratech, Inc.

Cornelia Kang-I Tsang

John Ulrich Knickerbocker

Bing Dang

Paul Stephen Andry

Edmund Juris Sprogis

Duixian Liu

Jae-Woong Nah

Li-Wen Hung

S Jay Chey

Timothy Charles Krywanczyk

Robert E Trzcinski

Matthew T Tiersch

Mohammed S Shaikh

Christopher Vincent Jahnes

Russell Alan Budd

John Michael Cotte

Jean-Olivier Plouchart

Brian Paul Gaucher

John Harold Magerlein

Chirag Suryakant Patel

Ullrich Richard Pfeiffer

Peter Jerome Sorce

Nils Deneke Hoivik

Janusz Grzyb

Ping-Chuan Wang

Timothy Joseph Dalton

Hariklia Deligianni

Timothy Dooling Sullivan

Bucknell Chapman Webb

Jeffrey Donald Gelorme

Emanuel Israel Cooper

Panayotis Constantinou Andricacos

Kenneth Jay Stein

Eric Peter Lewandowski

Michelle Leigh Steen

James Anthony Tornello

Keith Thomas Kwietniak

Daniel Guidotti

Michael Francis Lofaro

Various embodiments process semiconductor devices. In one embodiment, a release layer is applied to a handler. The release layer comprises at least one additive that adjusts a frequency of electro-magnetic radiation absorption property of the release layer. The additive comprises, for example, a 355 nm chemical absorber and/or chemical absorber for one of more wavelengths in a range comprising 600 nm to 740 nm. The at least one singulated semiconductor device is bonded to the handler. The at least one singulated semiconductor device is packaged while it is bonded to the handler. The release layer is ablated by irradiating the release layer through the handler with a laser. The at least one singulated semiconductor device is removed from the transparent handler after the release layer has been ablated.

Handler bonding and debonding for semiconductor dies

A bonded structure contains a substrate containing at least one feature, the substrate having a top surface; a first release layer overlying the top surface of the substrate, the first release layer being absorptive of light having a first wavelength for being decomposed by the light; an adhesive layer overlying the first release layer, and a second release layer overlying the adhesive layer. The second release layer is absorptive of light having a second wavelength for being decomposed by the light having the second wavelength. The bonded structure further contains a handle substrate that overlies the second release layer, where the handle substrate is substantially transparent to the light having the first wavelength and the second wavelength. Also disclosed is a debonding method to process the bonded structure to remove and reclaim the adhesive layer for re-use. In another embodiment a multi-step method optically cuts and debonds a bonded structure.

Double layer release temporary bond and debond processes and systems

Structures and methods are provided for temporarily bonding handler wafers to device wafers using bonding structures that include one or more releasable layers which are laser-ablatable using mid-wavelength infrared radiation.

Wafer debonding using mid-wavelength infrared radiation ablation

Package structures are provided for integrally packaging antennas with semiconductor RFIC (radio frequency integrated circuit) chips to form compact integrated radio/wireless communications systems that operate in the millimeter-wave and terahertz frequency ranges. For example, a package structure includes an RFIC chip, and an antenna package bonded to the RFIC chip. The antenna package includes a glass substrate, at least one planar antenna element formed on a first surface of the glass substrate, a ground plane formed on a second surface of the glass substrate, opposite the first surface, and an antenna feed line formed through the glass substrate and connected to the at least one planar antenna element. The antenna package is bonded to a surface of the RFIC chip using a layer of adhesive material.

Integration of area efficient antennas for phased array or wafer scale array antenna applications

A test probe structure having a planar surface and contact locations matched to test hardware is provided. The fabrication of the test probe structure addresses problems related to the possible deformation of base substrates during manufacture. Positional accuracy of contact locations and planarity of base substrates is achieved using dielectric layers, laser ablation, injection molded solder or redistribution layer wiring, and planarization techniques.

Test probe substrate

Methods are provided to form adhesive materials that are used to temporarily bond handler wafers to device wafers, and which enable mid-wavelength infrared laser ablation release techniques to release handler wafers from device wafers.

Adhesives for bonding handler wafers to device wafers and enabling mid-wavelength infrared laser ablation release

Methods are provided for handling a device wafer. For example, a method includes providing a stack structure having a device wafer, a handler wafer, and a bonding structure disposed between the device wafer and handler wafer, and irradiating the bonding structure with long-wavelength infrared energy to ablate the bonding structure.

Wafer debonding using long-wavelength infrared radiation ablation

A silicon chicklet pedestal for use in a wafer-level test probe of a wafer is provided and includes a main body, first and second opposing faces, and an array of vias formed through the main body to extend between the first and second faces, through which pairs of leads, respectively associated with each via at the first and second faces, are electrically connectable to one another.

Silicon chicklet pedestal

A through silicon via structure and a method of fabricating the through silicon via. The method includes: (a) forming a trench in a silicon substrate, the trench open to a top surface of the substrate; (b) forming a silicon dioxide layer on sidewalls of the trench, the silicon dioxide layer not filling the trench; (c) filling remaining space in the trench with polysilicon; after (c), (d) fabricating at least a portion of a CMOS device in the substrate; (e) removing the polysilicon from the trench, the dielectric layer remaining on the sidewalls of the trench; (f) re-filling the trench with an electrically conductive core; and after (f), (g) forming one or more wiring layers over the top surface of the substrate, a wire of a wiring level of the one or more wiring levels closest to the substrate contacting a top surface of the conductive core.

Through silicon via and method of fabricating same

Through silicon via for use in integrated circuit chips

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Mohegan Lake, NY, United States of America

Cornelia Kang-I Tsang