General Electric Company

Harris Corporation

Martin Marietta Corporation

Constantine A Neugebauer

Homer H Glascock, Ii

James F Burgess

Victor A Temple

Donald L Watrous

Harold F Webster

Kyung W Paik

Alexander J Yerman

James G McMullen

Robert J Wojnarowski

Wolfgang Daum

James A Loughran

Richard O Carlson

Robert J Satriano

Charles W Eichelberger

Herbert S Cole

Stanton Earl Weaver, Jr

Lionel M Levinson

Raymond Albert Fillion

Sayed-Amr A El-Hamamsy

Charles S Korman

Donald W Jones

Bernard Gorowitz

Eric J Wildi

Dante E Piccone

Michael Gdula

Roland T Girard

Francois D Martzloff

Anthony A Immorlica, Jr

David Leonard Mueller

Eugene L Bartels

Fadel A Selim

Martha M Neugebauer

Wivina A DeDoncker

Walter M Bryant

Guy L Babcock

A process for direct bonding a copper film to an yttria-doped aluminum nitride substrate comprises treating the substrate by preoxidation at elevated temperature to create an overlying thin film of Al.sub.2 O.sub.3, followed by step cooling to a lower temperature. A copper foil of thickness between 1.0 and 4.0 microns and generally perforated or otherwise foraminous, is eutectically direct bonded to the substrate by the known direct bond copper (DBC) process. The resultant article exhibits high thermal conductivity, low permittivity and high mechanical strength. The peel strength of the copper film on the AlN substrate exceeds the peel strengths previously attainable in the industry.

Direct bonding of copper to aluminum nitride substrates

In fabricating wafer scale integrated interconnects, a temporary or permanent dielectric layer and a pattern of electrical conductors are used to provide wafer scale integration or testing and burn-in. A resist can be used to cover the areas of IC pads on the wafer while the remainder of the pattern of electrical conductors is removed to provide for repair of the wafer scale integration structure. The pattern of electrical conductors may be configured so that the conductor lengths between at least some sub-circuits on a plurality of wafers are substantially electrically equal for signal propagation purposes; an additional wafer may be laminated to the wafer using an adhesive; controlled curfs may be cut into the wafer; and the wafer may be interconnected to an interface ring.

Wafer level integration and testing

Annealed copper foil (12) is coated with chromium film (16), followed by coating with an appropriate thickness of gold film (14) and is thermocompression bonded to an aluminum metallized substrate (18) on a silicon chip (30) to provide solderable, high current contacts to the chip. The foil is formed into appropriate electrical network-contact patterns (40) and is bonded to the silicon chip only where aluminum metallization exists on the chip. Leaf (wing) portions (46) of the foil extend beyond the boundaries of the silicon chip for subsequent retroflexing over the foil to provide electrical contact at predesignated locations (49). External contacts to the foil are made by penetrating through a ceramic lid positioned directly above the foil area. Thus, direct thermocompression bonding of a principally copper foil to aluminum semiconductor pads can replace current gold detent/bump connections by securing a copper conductor to a silicon chip through an intermetallic AuAl.sub.2 link and an aluminum stratum.

Direct thermocompression bonding for thin electronic power chips

An integrated heat sink module includes a sinuously channeled base and a bonded top surface electrode that is dielectrically isolated from the base. The top surface electrode acts as a common modular electrode capable of conducting heat to an ultimate cooling medium with no intervening thermal barrier. Constrained copper technology (CCT) is employed to ensure that the relatively low effective temperature coefficient of expansion of the channel base is acquired by the channel cover, which is the dielectrically (but not thermally) insulated top surface, and that the common electrode is integrated with, by forming a part of, the fluid channel in the base. The heat sink weight is reduced significantly by the channeling, while use of the CCT technology ensures high reliability and integrity of the module.

Integrated heat sink having a sinuous fluid channel for the thermal

A moisture-proof integrated circuit module includes at least one integrated circuit component in a high density interconnect (HDI) structure fabricated by applying to a substrate successive multiple ply sequences having a plurality of via holes therein. The sequences overlie the component(s) and the module substrate, and each sequence includes a dielectric film and a plurality of lands comprised of metal that extends into the vias of the sequence to provide electrical interconnections. The module includes at least one moisture barrier film to prevent penetration of moisture through the module to the circuit component(s).

Moisture-proof electrical circuit high density interconnect module and

A hermetic semiconductor package having a ceramic lid with the device leads extending vertically through the lid is disclosed. The leads are mechanically retained within the apertures in the lid and direct bonded to the lid to provide a hermetic seal and a substantial lead density.

Hermetic package and packaged semiconductor chip having closely spaced

Method for forming semiconductor electrical contacts using metal foil

A hermetic semiconductor package includes a ceramic lid with the device leads extending vertically through the lid. The leads are mechanically retained within the apertures in the lid and direct bonded to the lid to provide a hermetic seal and a substantial lead density.

Batch assembly methods for high density packaging of power semiconductor chips in hermetic thin packagings includes providing silicon chip arrays with thermocompressively bonded foil contacts, preparing ceramic lid arrays which contain upper surface and lower margin direct-bonded copper coverings and through-the-lid high current spherical conductors, coining Cu/Mo/Cu or copper cup arrays, die mounting within each respective cup a respective semiconductor chip, superpositionally registering a lid array with a strip form of cup array, and solder reflowing to hermetically seal all hermetic thin packagings within a registered set of cup and lid arrays.

Batch assembly of high density hermetic packages for power semiconductor

A hermetically sealed package for a semiconductor device includes a lid through which the leads of the device extend vertically away from the chip through an aperture in the lid which is hermetically sealed by the external terminal or electrode. The package is compact, lightweight and free of magnetic materials.

Method of forming a hermetic package having a lead extending through an

A hermetic, high current package for a semiconductor device includes wide flat leads which are bonded to the contact pads of the device and formed to extend through apertures in an insulating lid. The lid is sealed to a base and the apertures around the leads are sealed with solder to provide the hermetic package. This package limits lateral current flow in the contact pads of the semiconductor device to relatively low levels which ensure the integrity of the contact pads.

Method of packaging a semiconductor chip in a low inductance package

Hermetic package having a lead extending through an aperture in the

A composite structure comprising a symmetric bimetallic laminate bonded to a separate substrate is provided by eutectic bonding the bimetallic laminate to the substrate. A variety of beneficial structures can be provided.

Direct bonded symmetric-metallic-laminate/substrate structures

A package for a two-switching-device half bridge circuit comprises an insulating substrate having first, second and third external power terminals along with control terminals bonded to the substrate. The power terminals are configured to provide a straight-through-the package current path from the first external power terminal to the second or common external power terminal and from the second or common external power terminal to the third external power terminal. The control terminals are preferably Kelvin terminal pairs in order to minimize feedback from the power current paths to the control circuits. The power devices are preferably bonded to the first external power terminal and the second external power terminal, respectively, with their connections respectively to the second power terminal and third power terminal substantially identical in order to provide power current paths through the package having substantially identical electrical and thermal impedances. This half bridge package is appropriate for use in high performance, high frequency, half bridge circuits.

Half bridge device package, packaged devices and circuits

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Schenectady, NY, United States of America

Constantine A Neugebauer