National Semiconductor Corporation

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Constantin Bulucea

Sandeep Raj Bahl

Prasad Chaparala

Jeng-Jiun Yang

Fu-Cheng Wang

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D Courtney Parker

Rebecca Rossen

Michael J Grubisich

Peter B Johnson

Chih Sieh Teng

Chin-Miin Shyu

Richard A Blanchard

Sameer P Pendharkar

Sheldon Aronowitz

Philipp Lindorfer

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Guru Mathur

John Lin

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Yongxi Zhang

Zachary K Lee

Esin Dermirlioglu

Andrew Derek Strachan

Terry Dyer

David Courtney Parker

Jim McGinty

Daniel C Kerr

Mark A Grant

A semiconductor device contains an LDNMOS transistor with a lateral n-type drain drift region and a p-type RESURF region over the drain drift region. The RESURF region extends to a top surface of a substrate of the semiconductor device. The semiconductor device includes a shunt which is electrically coupled between the RESURF region and a low voltage node of the LDNMOS transistor. The shunt may be a p-type implanted layer in the substrate between the RESURF layer and a body of the LDNMOS transistor, and may be implanted concurrently with the RESURF layer. The shunt may be through an opening in the drain drift region from the RESURF layer to the substrate under the drain drift region. The shunt may be include metal interconnect elements including contacts and metal interconnect lines.

Structures to avoid floating resurf layer in high voltage lateral devices

Structures to avoid floating RESURF layer in high voltage lateral devices

A semiconductor structure, which serves as the core of a semiconductor fabrication platform, has a combination of empty-well regions and filled-well regions variously used by electronic elements, particularly insulated-gate field-effect transistors ('IGFETs'), to achieve desired electronic characteristics. A relatively small amount of semiconductor well dopant is near the top of an empty well. A considerable amount of semiconductor well dopant is near the top of a filled well. Some IGFETs (, and) utilize empty wells (, and) in achieving desired transistor characteristics. Other IGFETs (, and) utilize filled wells (, and) in achieving desired transistor characteristics. The combination of empty and filled wells enables the semiconductor fabrication platform to provide a wide variety of high-performance IGFETs from which circuit designers can select particular IGFETs for various analog and digital applications, including mixed-signal applications.

Configuration and fabrication of semiconductor structure using empty and filled wells

An asymmetric insulated-gate field-effect transistor (or) has a source (or) and a drain (or) laterally separated by a channel zone (or) of body material (or) of a semiconductor body. A gate electrode (or) overlies a gate dielectric layer (or) above the channel zone. A more heavily doped pocket portion (or) of the body material extends largely along only the source. The source has a main source portion (M orM) and a more lightly doped lateral source extension (E orE). The drain has a main portion (M orM) and a more lightly doped lateral drain extension (E orE). The drain extension is more lightly doped than the source extension. The maximum concentration of the semiconductor dopant defining the two extensions occurs deeper in the drain extension than in the source extension. Additionally or alternatively, the drain extension extends further laterally below the gate electrode than the source extension. These features enable the threshold voltage to be highly stable with operational time.

Structure and fabrication of asymmetric field-effect transistor having asymmetric channel zone and differently configured source/drain extensions

An insulated-gate field-effect transistor (U) utilizes an empty-well region for achieving high performance. The concentration of the body dopant reaches a maximum at a subsurface location no more than 10 times deeper below the upper semiconductor surface than the depth of one of a pair of source/drain zones (and), decreases by at least a factor of 10 in moving from the subsurface location along a selected vertical line (U) through that source/drain zone to the upper semiconductor surface, and has a logarithm that decreases substantially monotonically and substantially inflectionlessly in moving from the subsurface location along the vertical line to that source/drain zone. Each source/drain zone has a main portion (M orM) and a more lightly doped lateral extension (E orE). Alternatively or additionally, a more heavily doped pocket portion () of the body material extends along one of the source/drain zones.

Semiconductor architecture having field-effect transistors especially suitable for analog applications

The Si substrate of a group III-N HEMT is formed in layers that define a p-n junction which electrically isolates an upper region of the Si substrate from a lower region of the Si substrate. As a result, the upper region of the Si substrate can electrically float, thereby obtaining a full buffer breakdown voltage, while the lower region of the Si substrate can be attached to a package by way of a conductive epoxy, thereby significantly improving the thermal conductivity of the group III-N HEMT and minimizing undesirable floating-voltage regions.

Group III-nitride HEMT with multi-layered substrate having a second layer of one conductivity type touching a top surface of a first layers of different conductivity type and a method for forming the same

The buffer breakdown of a group III-N HEMT on a p-type Si substrate is significantly increased by forming an n-well in the p-type Si substrate to lie directly below the metal drain region of the group III-N HEMT. The n-well forms a p-n junction which becomes reverse biased during breakdown, thereby increasing the buffer breakdown by the reverse-biased breakdown voltage of the p-n junction and allowing the substrate to be grounded. The buffer layer of a group III-N HEMT can also be implanted with n-type and p-type dopants which are aligned with the p-n junction to minimize any leakage currents at the junction between the substrate and the buffer layer.

Group III-nitride HEMT having a well region formed on the surface of substrate and contacted the buffer layer to increase breakdown voltage and the method for forming the same

An asymmetric insulated-gate field effect transistor (U orU) provided along an upper surface of a semiconductor body contains first and second source/drain zones (andorand) laterally separated by a channel zone (or) of the transistor's body material. A gate electrode (or) overlies a gate dielectric layer (or) above the channel zone. A pocket portion (or) of the body material more heavily doped than laterally adjacent material of the body material extends along largely only the first of the S/D zones and into the channel zone. The vertical dopant profile of the pocket portion is tailored to reach a plurality of local maxima (---) at respective locations (PH--PH-) spaced apart from one another. The tailoring is typically implemented so that the vertical dopant profile of the pocket portion is relatively flat near the upper semiconductor surface. As a result, the transistor has reduced leakage current.

Configuration and fabrication of semiconductor structure having asymmetric field-effect transistor with tailored pocket portion along source/drain zone

Insulated-gate field-effect transistors ('IGFETs'), both symmetric and asymmetric, suitable for a semiconductor fabrication platform that provides IGFETs for analog and digital applications, including mixed-signal applications, utilize empty-well regions in achieving high performance. A relatively small amount of semiconductor well dopant is near the top of each empty well. Each IGFET (, or) has a pair of source/drain zones laterally separated by a channel zone of body material of the empty well (, or). A gate electrode overlies a gate dielectric layer above the channel zone. Each source/drain zone (, or) has a main portion (M,M,M,M,M,M,M,M,M,M,M, orM) and a more lightly doped lateral extension (E,E,E,E,E,E,E,E,E,E,E, orE). Alternatively or additionally, a more heavily doped pocket portion (or) of the body material extends along one of the source/drain zones. When present, the pocket portion typically causes the IGFET to be an asymmetric device.

Structure and fabrication of field-effect transistor using empty well in combination with source/drain extensions or/and halo pocket

An insulated-gate field-effect transistor (V,V,V,V,W,U,V,W,, or) has a hypoabrupt vertical dopant profile below one (or) of its source/drain zones for reducing the parasitic capacitance along the pn junction between that source/drain zone and adjoining body material (or). In particular, the concentration of semiconductor dopant which defines the conductivity type of the body material increases by at least a factor of 10 in moving from that source/drain zone down to an underlying body-material location no more than 10 times deeper below the upper semiconductor surface than that source/drain zone. The body material preferably includes a more heavily doped pocket portion (or) situated along the other source/drain zone (or). The combination of the hypoabrupt vertical dopant profile below the first-mentioned source/drain zone, normally serving as the drain, and the pocket portion along the second-mentioned source/drain zone, normally serving as the source, enables the resultant asymmetric transistor to be especially suitable for high-speed analog applications.

A group of high-performance like-polarity insulated-gate field-effect transistors (, andor, and) have selectably different configurations of lateral source/drain extensions, halo pockets, and gate dielectric thicknesses suitable for a semiconductor fabrication platform that provides a wide variety of transistors for analog and/or digital applications. Each transistor has a pair of source/drain zones, a gate dielectric layer, and a gate electrode. Each source/drain zone includes a main portion and a more lightly doped lateral extension. The lateral extension of one of the source/drain zones of one of the transistors is more heavily doped or/and extends less deeply below the upper semiconductor surface than the lateral extension of one of the source/drain zones of another of the transistors.

Structure and fabrication of like-polarity field-effect transistors having different configurations of source/drain extensions, halo pockets, and gate dielectric thicknesses

A semiconductor structure is provided with (i) an empty well having relatively little well dopant near the top of the well and (ii) a filled well having considerably more well dopant near the top of the well. Each well is defined by a corresponding body-material region (or) of a selected conductivity type. The regions respectively meet overlying zones (and) of the opposite conductivity type. The concentration of the well dopant reaches a maximum in each body-material region no more than 10 times deeper below the upper semiconductor surface than the overlying zone's depth, decreases by at least a factor of 10 in moving from the empty-well maximum-concentration location through the overlying zone to the upper semiconductor surface, and increases, or decreases by less than a factor of 10, in moving from the filled-well maximum-concentration location through the other zone to the upper semiconductor surface.

Fabrication of semiconductor architecture having field-effect transistors especially suitable for analog applications

A semiconductor structure contains a bipolar transistor () and a spacing structure (-or-). The transistor has an emitter (), a base (), and a collector (). The base is formed with an intrinsic base portion (I), a base link portion (L), and a base contact portion (C). The intrinsic base portion is situated below the emitter and above material of the collector. The base link portion extends between the intrinsic base portion and the base contact portions. The spacing structure includes an isolating dielectric layer (-or-) and a spacing component. The dielectric layer extends along the upper semiconductor surface. The spacing component includes a lateral spacing portion (-or-) of largely non-monocrystalline semiconductor material, preferably polycrystalline semiconductor material, situated on the dielectric layer above the base link portion. Opposite first and second upper edges of the lateral spacing portion (-and-) laterally conform to opposite first and second lower edges (-and-) of the base link portion so as to determine, and thereby control, its length.

Configuration and fabrication of semiconductor structure having bipolar junction transistor in which non-monocrystalline semiconductor spacing portion controls base-link length

An insulated-gate field-effect transistor () provided along an upper surface of a semiconductor body contains a pair of source/drain zones (and) laterally separated by a channel zone (). A gate electrode () overlies a gate dielectric layer () above the channel zone. Each source/drain zone includes a main portion (M orM) and a more lightly doped lateral extension (E orE) laterally continuous with the main portion and extending laterally under the gate electrode. The lateral extensions, which terminate the channel zone along the upper semiconductor surface, are respectively largely defined by a pair of semiconductor dopants of different atomic weights. With the transistor being an asymmetric device, the source/drain zones constitute a source and a drain. The lateral extension of the source is then more lightly doped than, and defined with dopant of higher atomic weight, than the lateral extension of the drain.

Configuration and fabrication of semiconductor structure in which source and drain extensions of field-effect transistor are defined with different dopants

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