Advanced Micro Devices Corporation

Concetta E Riccobene

Carl Robert Huster

Bin Yu

William George En

Judy Xilin An

Dong-Hyuk Ju

Zoran Krivokapic

Scott D Luning

Donald L Wollesen

Srinath Krishnan

Wei Long

Tim Thurgate

Nga-Ching Wong

Ognjen Milic-Strkalj

Richard P Rouse

Xilin Judy An

A semiconductor-on-insulator (SOI) wafer. The wafer includes a silicon substrate, a buried oxide (BOX) layer disposed on the substrate, and an active layer disposed on the box layer. The active layer has an upper silicon layer disposed on a silicon-germanium layer. The silicon-germanium layer is disposed on a lower silicon layer. The silicon-germanium of the silicon-germanium layer is strained silicon-germanium and is about 200 &angst; to about 400 &angst; thick.

Semiconductor-on-insulator (SOI) wafer having a Si/SiGe/Si active layer and method of fabrication using wafer bonding

A device and method for making a semiconductor-on-insulator (SOI) structure having a leaky, thermally conductive material (LTCIM) layer disposed between a semiconductor substrate and a semiconductor layer.

Leaky, thermally conductive insulator material (LTCIM) in semiconductor-on-insulator (SOI) structure

An asymmetric retrograde HALO Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) includes a semiconductor substrate. A gate is formed over the substrate, the gate defining a channel thereunder in the substrate having a source side and a drain side. A retrograde HALO doped area is formed in the source side of the channel using tilted ion implantation. A source and drain are formed in the substrate adjacent to the source and drain sides of the channel. The asymmetrical doping arrangement provides the specified level of off-state leakage current without decreasing saturation drive current and transconductance.

Asymmetric retrograde halo metal-oxide-semiconductor field-effect transistor (MOSFET)

Channel carrier mobility is increased by reducing gate/gate dielectric interface roughness, thereby reducing surface scattering. Embodiments include depositing a layer of silicon by selective epitaxy prior to gate oxide formation to provide a substantially atomically smooth surface resulting in a smoother interface between the gate polysilicon and silicon oxide after oxidation.

Selective epitaxy to reduce gate/gate dielectric interface roughness

A transistor on an SOI wafer has a subsurface recombination area within its body. The recombination area includes one or more doped subsurface islands, the doped islands having the same conductivity type as that of a source and a drain on opposite sides of the body, and having an opposite conductivity type from the remainder of the body. The doped subsurface island(s) may be formed by a doping implant into a surface semiconductor layer, for example through an open portion of a doping mask, the opening portion created for example by removal of a dummy gate. The doping of the islands may be performed so that the doping level of the island(s) is approximately the same as that of the body, thus enabling both Shockley-Read-Hall (SRH) and Auger recombination to take place.

SOI device with body recombination region, and method

A semiconductor device and a method of forming same are disclosed. The device includes an SOI wafer including a semiconductor layer, a substrate and a buried insulator layer therebetween. The semiconductor layer includes a source region, a drain region, and a body region disposed between the source and drain regions. At least one of the source and drain regions includes an epitaxially raised region. A gate is on the semiconductor layer, the gate being operatively arranged with the source, drain, and body regions to form a transistor. The at least one of the source and drain regions including the epitaxially raised region includes a silicide region spaced apart from the body region by about 200 to about 1000 Angstroms.

Raised S/D region for optimal silicidation to control floating body effects in SOI devices

According to the invention, a silicon-on-insulator (SOI) device and a method of constructing the device is disclosed. The SOI device has a substrate with a BOX layer disposed on the upper surface of the substrate. The BOX has an upper surface and a cavity extending from the upper surface partially therein. An active layer is disposed on the upper surface of BOX layer and extends into the cavity.

Removal of heat from SOI device

A silicon-on-insulator (SOI) transistor. The SOI transistor includes a germanium implanted source and drain having a body disposed therebetween, and a gate disposed on the body, the germanium being implanted at an angle such that the source has a concentration of germanium at a source/body junction and the gate shields germanium implantation in the drain adjacent a drain/body junction resulting in a graduated drain/body junction. Also disclosed is a method of fabricating the SOI transistor.

Silicon-on-insulator transistors with asymmetric source/drain junctions formed by angled germanium implantation

A method is provided for accurately determining the junction depth of silicon-on-insulator (SOI) devices. Embodiments include determining the junction depth in an SOI device under inspection by measuring the threshold voltage of its &ldquo;bottom transistor&rdquo; formed by its source and drain regions together with its substrate acting as a gate. The threshold voltage of the bottom transistor of an SOI device varies with its junction depth in a predictable way. Thus, the junction depth of the inspected device is determined by comparing its bottom transistor threshold voltage with the bottom transistor threshold voltage of corresponding reference SOI devices of known junction depth to find a match. For example, simulated SOI devices with the same characteristics as the inspected device, whose junction depth and bottom transistor threshold voltages have been previously calculated, are used as a &ldquo;reference library&rdquo;. If the bottom transistor threshold voltage of the inspected device has about the same value as that of a particular one of the reference devices, then the inspected device has the junction depth of that particular reference device. Thus, junction depth of the inspected SOI device is accurately determined by a simple electrical measurement of threshold voltage.

Method for measuring source and drain junction depth in silicon on insulator technology

A method of forming a semiconductor-on-insulator (SOI) wafer. The method includes the steps of providing a first wafer, the first wafer having a silicon substrate and an oxide layer disposed thereon; providing a second wafer, the second wafer having a silicon substrate, the substrate of the second wafer having a silicon-germanium layer disposed thereon, a silicon layer disposed on the silicon-germanium layer and an oxide layer disposed on the silicon layer; wafer bonding the first and second wafers; and removing an undesired portion of the substrate from the second wafer to form an upper silicon layer. The resulting SOI wafer structure is also disclosed.

Method of fabrication of semiconductor-on-insulator (SOI) wafer having a Si/SiGe/Si active layer

A field effect transistor ( ) having a source region ( ) and a drain region ( ) includes a source side halo region ( ) formed at a junction between the source region and a channel region to substantially interrupt off state leakage current. The source side halo region is formed by implanting ( ) first doping ions near the surface at the source side of the channel and implanting ( ) second doping ions deeper in the channel, near the depth of a source extension ( ). In this manner, optimization of leakage current of the field effect transistor is made independent of the drive current of the field effect transistor.

Optimized single side pocket implant location for a field effect transistor

A method of reducing the gate resistance in a semiconductor device forms a gate in the semiconductor device followed by the creation of a silicide region on top of the gate. During the initial formation of the silicide region on the gate, formation of silicide on source/drain areas of the semiconductor device is prevented by a shielding material. The shielding material is then removed and additional silicide is created, forming silicide regions on the source/drains and increasing the thickness of the silicide over the gate, thereby lowering the gate resistance.

Dual silicide process to reduce gate resistance

A method is provided for directly measuring the source/drain resistance of a metal oxide semiconductor (MOS) device. Embodiments include partially deconstructing a typical MOS device by removing its gate and gate oxide from the substrate, as by etching, while preserving its gate sidewall spacer (typically silicon nitride). A sacrificial oxide spacer is formed on the nitride spacer, as by anisotropically etching a deposited oxide layer, and the area surrounding the sacrificial oxide spacer is filled with a layer of nitride. The sacrificial oxide spacer is then selectively etched to expose a portion of the main surface of the substrate and leave the nitride spacer and layer, thus creating a location near the edge of a source/drain region for a metal contact to be formed, as by chemical vapor deposition (CVD). The source/drain resistance of the device can then be directly and accurately measured by making electrical contact to the newly formed contact and a pre-existing source/drain contact on the same active area.

Formation of structure to accurately measure source/drain resistance

A method for manufacturing a field effect transistor (,) includes steps of forming a gate stack (,) on the surface (,) of a semiconductor substrate (,), and defining source/drain regions (,) on either side of the gate stack and a channel region (,) under the gate stack. The channel region has one end (,) proximate a first source/drain region and another end (,) proximate a second source/drain region. The method further includes forming a masking layer (,) on the surface of the semiconductor substrate. The masking layer has a nominal alignment position and a misalignment tolerance. The method still further includes implanting doping ions in the semiconductor substrate to asymmetrically dope the field effect transistor, including selecting a tilt angle and a rotation angle (B, D, F, H) sufficient to ensure shadowing of one end of the channel region from implantation of the doping ions.

Method for manufacturing asymmetric channel transistor

High drain capacitance is reduced, thereby increasing device speed, by forming transistors with a gate oxide having a thickness which is smaller at the drain region than at the source region. Embodiments include selectively ion implanting neutral impurities, such as silicon, geranium or argon, into and/or roughening the substrate surface to increase its oxidation rate proximate the contemplated source region and/or selectively ion implanting nitrogen to reduce its oxidation rate proximate the contemplated drain region. Other embodiments include etching a gate oxide layer having a first thickness to form a portion having a reduced second thickness proximate the contemplated drain region and thermally oxidizing to form a transition zone having a thickness gradually decreasing from the first thickness to the second thickness.

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Mountain View, CA, United States of America

Concetta E Riccobene