International Business Machines Corporation

Globalfoundries Inc.

Adeia Semiconductor Bonding Technologies Inc.

Conal Eugene Murray

Chih-Chao Yang

Kenneth Parker Rodbell

Thomas M Shaw

Ping-Chuan Wang

Vincent James McGahay

Christian Lavoie

Guy M Cohen

Cyril Cabral, Jr

Hazara Singh Rathore

Xiao Hu Liu

Ronald Gene Filippi, Jr

Gregory M Fritz

Louis L Hsu

Louis C Hsu

Michael Wayne Lane

Lynne Marie Gignac

Paul Stephen McLaughlin

Jason Paul Gill

Giovanni Fiorenza

Lawrence Alfred Clevenger

Jeffrey W Sleight

Michael S Gordon

Sarunya Bangsaruntip

Fenton Read McFeely

Habib Hichri

Anita Madan

Jawahar P Nayak

Simon Gaudet

Carl John Radens

Michael A Guillorn

Sampath Purushothaman

Timothy Joseph Dalton

Matthew Earl Colburn

Satyanarayana Venkata Nitta

Chandrasekhar Narayan

Robert L Wisnieff

Oh-Jung Kwon

Robert Rosenberg

Ricardo Alves Donaton

Michael Joseph Rooks

Sujatha Sankaran

Donghun Kang

Kriteshwar Kaur Kohli

Oliver C Wells

Henry Tang

Kwong-Hon Wong

Christophe Detavenier

Stephen W Bedell

Theodorus E Standaert

Alfred Grill

Judson Robert Holt

Hariklia Deligianni

Katherine Lynn Saenger

Fei Liu

Jack Oon Chu

Jeng-Bang Yau

Chandrasekharan Kothandaraman

Thomas N Adam

Sandra Guy Malhotra

Ronald G Filippi

Stephen Mark Rossnagel

Steven John Koester

Yun-Yu Wang

Tom C Lee

Anil Kumar Chinthakindi

Panayotis Constantinou Andricacos

Hormazdyar M Dalal

Brian L Ji

Oliver Desmond Patterson

Troy Lawrence Graves-Abe

Matthew S Angyal

Ismail C Noyan

Du Binh Nguyen

Birendra N Agarwala

Eric C Harley

Gregory Allen Northrop

Ageeth Anke Bol

Wilma Jean Horkans

Ernest N Levine

Christophe Detavernier

Dale Curtis McHerron

Philippe M Vereecken

Keith Thomas Kwietniak

Steffen K Kaldor

Gerald Matusiewicz

David F Heidel

Mohammed Fazil Fayaz

Andrew Lu

Philippe Mark Vereecken

Kevin E Mello

Conrad A Barile

Teresa L Pinto

Matthew Wayne Oonk

Jonathan Rullan

Mary Yvonne Lanzerotti Wisniewski

Henry Hong Ki Tang

Thedorus Eduardos Standaert

Richard Andre′ Wachnik

Anne L Petrosky

A method for measuring alpha particle emissions may include obtaining a wafer emission rate, wherein the wafer emission rate is measured with a counter. The method may further include covering the wafer with a metal mesh grounded to a cathode of the counter wherein the metal mesh is grounded to the cathode outboard of the wafer and obtaining a mesh and wafer emission rate, wherein the mesh and wafer emission rate is measured with the counter. The method may further include replacing the wafer with a wafer carcass, obtaining a wafer carcass and mesh emission rate, and calculating a wafer carcass emissivity.

Evaluation of wafer carcass alpha particle emission

A semiconductor interconnect structure having a first electrically conductive structure having a plurality of bottom portions; a dielectric capping layer, at least a portion of the dielectric capping layer being in contact with a first bottom portion of the plurality of bottom portions; and a second electrically conductive structure in electrical contact with a second bottom portion of the plurality of bottom portions. A method of forming the interconnect structure is also provided.

Semiconductor device with reduced via resistance

A metal interconnect structure can be fabricated within an integrated circuit (IC). A recess can be created in an IC dielectric layer and a surface modulation liner can be formed by depositing two different metallic elements onto the surfaces of the recess. One metallic element can have a standard electrode potential greater than a standard electrode potential of an interconnect metal, and the other metallic element can have a standard electrode potential less than the standard electrode potential of the interconnect metal. A metal interconnect structure can be formed by filling the remainder of the recess with interconnect metal, which is physically separated from the dielectric layer by the surface modulation liner. The surface topography of the metal interconnect structure can be modulated with a polishing process, by removing a top portion of the interconnect metal and a top portion of the surface modulation liner.

Modulating metal interconnect surface topography

Methods for forming high aspect-ratio conductive regions of a metallization network with reduced grain boundaries are described. Aspects of the invention include forming a trench in a dielectric material on the substrate. A conductive material is formed in the trench, wherein the conductive material includes a first grain boundary level. Portions of the dielectric material are removed to expose sidewalls of the conductive material. The conductive material is annealed to reduce the first grain boundary level.

Controlling grain boundaries in high aspect-ratio conductive regions

A semiconductor interconnect structure that has a first portion included in an upper interconnect level and a second portion included in a lower interconnect level. The semiconductor interconnect structure has a segment of dielectric capping material that is in contact with the bottom of the first portion, which separates, in part, the upper interconnect level from a lower interconnect level. The second portion is in electrical contact with the first portion.

A method of forming an electrical transmission structure that includes forming an opening through an interlevel dielectric layer to expose at least one electrically conductive feature and forming a shield layer on the opening. A gouge is formed in the electrically conductive feature through the opening using a subtractive method during which the shield layer protects the interlevel dielectric layer from being damaged by the subtractive method. A contact is formed within the opening in electrical communication with the at least one electrically conductive feature.

Reducing contact resistance in vias for copper interconnects

A method of fabricating a semiconductor interconnect structure by providing a semiconductor structure with a dielectric layer with and an embedded electrically conductive structure. A dielectric capping layer and a metal capping layer separating a second dielectric layer located above the first dielectric layer. The segment of metal capping layer covers at least a portion of a top surface of the first electrically conductive structure. Exposing parts of both the first electrically conductive structure and the dielectric capping layer by forming an opening in the second dielectric layer and the metal capping layer. Forming a second electrically conductive structure in the opening, such that (i) the second electrically conductive structure is located over part of the dielectric capping layer, and (ii) the second electrically conductive structure is in electrical contact with the first electrically conductive structure.

A method for manufacturing a semiconductor device includes forming a trench in at least one dielectric layer; and forming an interconnect structure in the trench, wherein forming the interconnect structure includes forming a first conductive layer on a bottom surface of the trench, and partially filling the trench, and forming a second conductive layer on the first conductive layer, and filling a remaining portion of the trench, wherein the second conductive layer comprises a different material from the first conductive layer, and wherein an amount of the first conductive layer in the trench is controlled so that an aspect ratio of the second conductive layer has a value that is determined to result in columnar grain boundaries in the second conductive layer.

Hybrid interconnects and method of forming the same

A method for manufacturing a semiconductor device includes conformally depositing a liner layer on a top surface of a dielectric layer, and on sidewall and bottom surfaces of an opening in the dielectric layer, annealing the liner layer, wherein the annealing is performed in at least one of a nitrogen (N) and ammonia (NH) ambient, at a temperature of about 60&#xb0; C. to about 500&#xb0; C., and at a power of about 200. Watts to about 4500. Watts, and forming a conductive layer on the liner layer on the top surface of the dielectric layer, and on the liner layer in a remaining portion of the opening.

Method for forming improved liner layer and semiconductor device including the same

Embodiments of the present invention provide integrated circuits and methods for activating reactions in integrated circuits. In one embodiment, an integrated circuit is provided having reactive material capable of being activated by electrical discharge, without requiring a battery or similar external power source, to produce an exothermic reaction that erases and/or destroys one or more semiconductor devices on the integrated circuit.

Activating reactions in integrated circuits through electrical discharge

Growing community of inventors

Yorktown Heights, NY, United States of America

Conal Eugene Murray