Advanced Micro Devices Corporation

Colin D Hatchard

Richard C Blish

Ian Morgan

J Courtney Black

David E Lewis

Michael David Fliesler

Daniel Yim

Pramod D Patel

Method for stepping identification and bond pad crater jeopardy identification in integrated circuits and apparatus which performs the method, A unique device, a polysilicon meander, is formed under each bond pad in the integrated circuit device. Connected to the meander is circuitry for determining the electrical, and hence mechanical, integrity of the meander. Failure of the meander by reason of microcrack formation in the several layers under the meander is detected by the high resistance of the meander. The circuitry will also resolve any potential mismatch between the actual mask revision of the integrated circuit and the corresponding revision of the test program.

Method and apparatus to achieve bond pad crater sensing and stepping identification in integrated circuit products

The present invention is a method for providing chip scale package. The method of the present invention includes providing a die with a first side, a second side, and a plurality of edges; applying a substance which protects against electrostatic discharge to the first side of the die and to the plurality of edges; and providing components on the second side of the die. The method of the present invention protects the chip scale package from electrostatic discharges. Markings may also be placed on the substance without damaging the chip in the package.

Method to improve chip scale package electrostatic discharge performance and suppress marking artifacts

Method for bond pad crater jeopardy identification in integrated circuits, and apparatus which performs the method. The gate or gates of a transistor or transistors of an ESD device are formed under each bond pad in the integrated circuit device. Connected to the transistor is circuitry for determimg the electrical, and hence mechanical, integrity of the transistor. A reduction in current through the transistor, by reason of microcrack formation in the several layers under the transistor causing a gate or gates of the transistor to crack and fail, may detected, Location of at least a portion of the ESD device, for example the above transistor, reduces overall chip area by increasing device density.

Method and apparatus for achieving bond pad crater sensing and ESD protection integrated circuit products

Aspects for supporting thinning of a flip-chip device with reduced risk of breakage are described. An exemplary apparatus aspect includes a multi-layer integrated circuit device oriented in a flip-chip orientation, and a support substrate transparent to a light source of a predetermined wavelength. The apparatus further includes an adhesive, the adhesive affixing the multi-layer integrated circuit device to the support structure during thinning of the multi-layer integrated circuit device from a backside and sufficiently releasing the multi-layer integrated circuit device when exposed to the light source of the predetermined wavelength through the support substrate after thinning is completed to reduce breakage risk for the thinned multi-layer integrated circuit device.

Technique for reducing breakage of thinned flip-chip multi-layer integrated circuit devices

Method for implementing a multi-phase plastic package for electronic components, and packaged electronic components produced according to the method. The present invention contemplates the use of molding compounds having two or more discrete phases in a transfer molding process wherein a temperature differential is induced between the electronic component to be packaged and the mold of the molding apparatus prior to molding. Each of the molding compound phases, when used in a current transfer molding apparatus, generates a separate layer in the resultant package, and each of the resultant layers possesses certain unique properties. In its simplest implementation, the present invention provides a two-phase molding compound pellet which provides an outer layer containing mold release compounds to facilitate release of the completed packaged device from the mold, and an inner layer without mold release agents. Other implementations include multiple layers. One such implementation provides for an inner layer without flame retardants and a layer exterior to the inner layer containing flame retardants. In this manner, chemical interaction between the flame retardants and the encapsulated device is precluded. Other adjuncts may, with equal facility, be implemented in such additional layers as a given application may require.

Encapsulation method using non-homogeneous molding compound pellets

A system and method for marking a chip-scale package is disclosed. In one aspect, the chip-scale package includes a semiconductor die. The semiconductor die has an exposed portion substantially surrounded by the first coating. In this aspect, the method and system include applying a second coating to a first portion of the first coating and marking the second coating. The first coating is not completely penetrated by the marking. In a second aspect, the method and system include providing a chip-scale package. In this aspect, the method and system comprise providing a substrate, providing a semiconductor die coupled to a substrate, and providing a first coating. The semiconductor die has an exposed portion. The exposed portion is substantially surrounded by the first coating. In this aspect, the method and system further include providing a second coating substantially covering a first portion of the first coating. The second coating has a plurality of markings therein. The first coating is not completely penetrated by the plurality of markings.

System for marking electrophoretic dies while reducing damage due to electrostatic discharge

Method to improve internal package delamination and wire bond

The present invention provides a microprocessor, the microprocessor having a substrate with a first and a second side, the first and second sides being on opposite sides of the substrate. The microprocessor includes decoupling capacitors on the first side of the substrate; cache circuitry on the first side of the substrate; logic circuitry on the second side of the substrate; and a signal carrying means including a carrier substrate and wire bonds for carrying signals between the logic and cache circuitry.

Signal carrying means including a carrier substrate and wire bonds for

Method for implementing a multi-phase plastic package for electronic components, and packaged electronic components produced according to the method. The principles of the present invention contemplate electrostatically depositing an exceptionally uniform coating on electronic components, especially microchips, and more especially still, on integrated circuits prior to the encapsulation of the electronic components into plastic-packaged components. The coating, for instance applied to a completed leadframe assembly, including die and wire bonds, serves two purposes. It improves adhesion of the molding compound forming the package, thereby reducing the chances for delamination of the package. The coating also isolates the relatively fragile wire bonds, including their attachment points to the chip and the bonding pads and the leads, from chemical and metallurgical attack by the flame retardant found in many molding compounds.

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Campbell, CA, United States of America

Colin D Hatchard