Taiwan Semiconductor Manufacturing Comp. Ltd.

Clinton Chao

Tjandra Winata Karta

Mark Shane Peng

Szu Wei Lu

Chao-Shun Hsu

Shin-Puu Jeng

Chien-Hsiun Lee

Szu-Wei Lu

Kuo-Chin Chang

Ann Luh

Jerry Tzou

Chen-Shien Chen

Kim Hong Chen

Ming-Chung Sung

Hsu Ming Cheng

Louis Chaochiuan Liu

Chien Hsiun Lee

Mirng Ji Lii

Mirng-Ji Lii

Tsung-Ding Wang

Pei-Haw Tsao

Hsin-Yu Pan

Kai-Ming Ching

Hua-Shu Ivan Wu

Bo-I Lee

Tsorng-Dih Yuan

Chung-Yu Wang

Dean Wang

Fa-Yuan Chang

Chen-Yao Tang

Frank Hwang

Lewis Chu

C W Hsiao

Warpage and breakage of integrated circuit substrates is reduced by compensating for the stress imposed on the substrate by thin films formed on a surface of the substrate. Particularly advantageous for substrates having a thickness substantially less than about 150 &#x3bc;m, a stress-tuning layer is formed on a surface of the substrate to substantially offset or balance stress in the substrate which would otherwise cause the substrate to bend. The substrate includes a plurality of bonding pads on a first surface for electrical connection to other component.

Methods of manufacturing an integrated circuit having stress tuning layer

Integrated circuit having stress tuning layer

Various structures of a programmable semiconductor interposer for electronic packaging are described. An array of semiconductor devices having various values is formed in the interposer. A user can program the interposer and form a 'virtual' device having a desired value by selectively connecting various one of the array of devices to contact pads formed on the surface of the interposer. An inventive electronic package structure includes a standard interposer having an array of unconnected devices of various values and a device selection unit, which selectively connects various one of the array of devices in the standard interposer to an integrated circuit die encapsulated in the electronic package. Methods of forming the programmable semiconductor interposer and the electronic package are also illustrated.

Programmable semiconductor interposer for electronic package and method of forming

A silicon-based thin package substrate is used for packaging semiconductor chips. The silicon-based thin package substrate preferably has a thickness of less than about 200 &#x3bc;m. A plurality of traces is formed in the silicon-based thin package substrate, connecting BGA balls and solder bumps. A semiconductor chip may be mounted on the solder bumps. The silicon-based thin package substrate may be used as a carrier of semiconductor chips.

Silicon-based thin substrate and packaging schemes

A wafer level integrated circuit assembly method is conducted as follows. First, a mother device wafer with plural first posts is provided. The first posts are used for electrical connection and are made of copper according to an embodiment. Solder is sequentially formed on the first posts. The solder is preferably pre-formed on a wafer, and the locations of the solder correspond to the first posts of the mother device wafer. Consequently, the solder can be formed on or adhered to the first posts by placing the wafer having pre-formed solder onto the first posts. Plural dies having plural second posts corresponding to the first posts are placed onto the mother device wafer. Then, the solder is reflowed to bond the first and second posts, and the mother device wafer is diced.

Wafer level IC assembly method

A method of forming a stacked die structure is disclosed. A plurality of dies are respectively bonded to a plurality of semiconductor chips on a first surface of a wafer. An encapsulation structure is formed over the plurality of dies and the first surface of the wafer. The encapsulation structure covers a central portion of the first surface of the wafer and leaves an edge portion of the wafer exposed. A protective material is formed over the first surface of the edge portion of the wafer.

Method of forming stacked-die packages

Method of manufacturing integrated circuit having stress tuning layer

A method for fabricating a semiconductor device is provided which includes providing a first device, a second device, and a third device, providing a first coating material between the first device and the second device, the first coating material being uncured, providing a second coating material between the second device and the third device, the second coating material being uncured, and thereafter, curing the first and second coating materials in a same process.

Method for stacking devices

A method of forming an integrated circuit structure is provided. The method includes providing an interposer wafer; mounting the interposer wafer onto a handling wafer; thinning a backside of the interposer wafer; removing the handling wafer from the interposer wafer after the step of thinning; securing the interposer wafer on a fixture; and bonding a die on the interposer wafer.

Process and apparatus for wafer-level flip-chip assembly

A silicon-based thin package substrate is used for packaging semiconductor chips. The silicon-based thin package substrate preferably has a thickness of less than about 200 &#x3bc;m. A plurality of traces are formed in the silicon-based thin package substrate, connecting BGA balls and solder bumps. A semiconductor chip may be mounted on the solder bumps. The silicon-based thin package substrate may be used as a carrier of semiconductor chips.

A method of packaging integrated circuit structures is provided. The method includes providing a wafer having bonding conductors on a surface of the wafer, and applying a compound underfill onto the surface of the wafer. The compound underfill includes an underfill material and a flux material. A die is then bonded on the wafer after the step of applying the compound underfill, wherein solder bumps on the die are joined with the bonding conductors.

Wafer-level flip-chip assembly methods

Growing community of inventors

Hsinchu, Taiwan

Clinton Chao