Hewlett-packard Company

Other

Clinton C Chao

Jacques Leibovitz

Kenneth D Scholz

Maria L Cobarruviaz

Daniel J Miller

Richard C Ruby

V K Nagesh

Voddarahalli K Nagesh

Timothy V Harper

Eric S Schneider

John C Wynbeek

John P Scalia

Hubert A VanderPlas

Edith P Prather

Kim K Chen

Howard H Nakano

A multilayer ceramic device has top and bottom green ceramic layers machined and fired. Intermediate green ceramic layers are machined, have conductors laid down in the machined areas, are laminated, and are fired to form an enclosure layer. The areas of the layers which will be in contact with each other are coated with a bonding agent. The layers are aligned and bonded to form a structure having arbitrarily shaped, interior channels adjacent to the top and bottom layers which are not subject to detrimental nonplanarities.

Planar multilayer ceramic structures with near surface channels

A method of forming standoff spacer pedestals on a device above the substrate by supporting the electronic device with the standoff spacer pedestals during solder reflow and bonding. Generally, the method comprising the steps of adhering at least one layer of film solder resist on the substrate, and eliminating the undesired portions of dry film solder resist to form the pedestals.

Spacing control in electronic device assemblies

A method for fabricating layers permits the accurate removal of surface material in a multi-layer multi-chip carrier. An intermediate layer of solid vias is deposited over a circuit layer attached to a substrate. The layer can be filled with a dielectric material. The substrate is attached to a substrate holder such that the intermediate layer is exposed, and the substrate holder is placed onto a rotating platen polisher with the intermediate layer facing the platen surface. Tooling presses the intermediate layer against the rotating polishing platen, allowing the substrate holder and substrate to rotate with three degrees of angular freedom, letting the substrate and intermediate layer self-align to the polishing platen in order to uniformly remove material from the intermediate layer surface. A second circuit layer can be formed on the resulting structure. The foregoing steps can be iterated to build a multi-layer structure of circuit layers separated by uniformly thick dielectric and via layers. As an alternative method, substrate attached to a substrate holder is placed against the platen surface of a shaking polisher, allowing the substrate and substrate holder to self-align to the polishing platen. In a third embodiment, where metal irregularities exist along the intermediate layer surface, wiping the surface evenly with cloth soaked in an appropriate etchant can uniformly remove the unwanted metal irregularities.

Multi-layer fabrication in integrated circuit systems

A specialized etching method for producing fine-geometry gold circuit structures. Production thereof is accomplished by maintaining a constant gold etching rate. Metal etching normally slows as the amount of dissolved gold (a reaction product of the etching process) increases. To remove the dissolved gold, one method involves cooling the etchant to precipitate a gold complex therefrom. The remaining, recovered etchant is then heated and made available for continued etching. Another method involves a cathode/anode assembly which is immersed in the etchant. Activation of the assembly recovers metallic gold and regenerates the etchant. These methods, when used continuously or periodically in a dip or spray etching system, maintain a constant etching rate. As a result, fine-geometry circuit structures may be accurately produced while minimizing material costs (e.g. etchant use) and minimizing the production of undesirable waste products and disposal expenses associated therewith.

Controlled etching process for forming fine-geometry circuit lines on a

A method for fabricating high density multi-chip carriers for integrated circuits includes the steps of forming a circuit pattern on a substrate, depositing a composite metal layer and a photoresist layer over the circuit pattern, forming apertures in the photoresist layer, forming solid metal vias in the apertures and, then, removing the photoresist layer. After removal of the first photoresist layer, a second photoresist layer is deposited over the solid vias and the circuit pattern. With the second photoresist layer in place, unprotected portions of the composite layer are etched away. Then, the second photoresist layer is stripped away. Next, a layer of photosensitive dielectric material is formed over the structure and, finally, sufficient portions of the photosensitive dielectric material are removed to expose the top surfaces of the solid vias.

Methods for forming high density multi-chip carriers

A method of forming solid copper vias in a dielectric layer permits stacked vias in a multi-chip carrier. A dielectric layer is deposited over a substrate and lines of a first interconnect layer formed on the substrate. An aperture formed in the dielectric layer is filled with copper by deposition to form a hollow via. Using a photoresist mask, the hollow via is filled solid by electroplating a second amount of copper. The photoresist is then stripped and excess copper extending from the via is polished flat. A second interconnect layer can be formed on the resulting structure. The foregoing steps can be iterated to build a multi-layer structure with stacked vias.

Stacked solid via formation in integrated circuit systems

An interconnection system and method for linking electronic devices such as semiconductor chips. Inner leads of a tape automated bonding frame are aligned with pads on the semiconductor chip. Inner lead bonding fixes the lead frame to the chip. Outer leads of the tape automated bonding frame are brought into an overlapping relationship with conductive traces on a substrate. Rather than microbonding the outer leads to the traces of the substrate, bond wires are attached to the outer leads and the traces, thereby allowing electrical communication of input and output signals therebetween. In one embodiment, the tensile strength of the bond wires is greater than that of the outer leads. In a second embodiment, the bond strength of the wire to the outer lead is greater than the bond strength of the wire to the substrate trace.

Tape automated bonding system which facilitate repair

A method of forming solid copper vias in a dielectric layer permits stacked up vias in a multi-layer multi-chip carrier. An conducting layer is deposited over a substrate and lines of a first interconnect layer formed on the substrate. An aperture formed in a photoresist layer over said lines is filled with copper by electroplating to form a solid via. The via can be polished until its top is flat. Using a photoresist mask, the conductive layer used for electroplating is removed between the lines. A dielectric layer is then formed over the lines and via. A bulge in the dielectric over the via is removed by etching through an aperture defined in a photoresist layer, which is then stripped. A second interconnect layer can be formed on the resulting structure. The foregoing steps can be iterated to build a multi-layer structure with stacked up vias.

A system and method of interconnecting a first tape automated bonding frame to a substrate so as to facilitate replacement by a second automated bonding frame. The automated bonding frame is formed to include a plurality of signal leads having a pattern of outer lead ends. A semiconductor chip is attached to the inner lead ends of the frame. Connection sites are formed on the substrate to correspond to the pattern of outer lead ends. The substrate bonds of the connection sites to the substrate have a first bonding strength. The outer lead ends are then attached to the connection sites to achieve a second bonding strength less than the first bonding strength. Thus, an application of force on the outer lead ends tends to separate the outer lead ends from the connection sites while leaving the substrate bonds intact. Preferably, the tensile strength of the signal leads is less than both of the above-described bonding strengths. In this manner, the signal leads can be broken prior to peeling of the outer lead ends from the connection sites of the substrate.

Hierarchical tape automated bonding method

A chip carrier for carrying integrated circuit chips is provided. Instead of placing individual circuit components either in the chips or next to them, the components are placed in or near the substrate of the chip carrier. This frees up expensive real-estate for logic chips at the chip level presently occupied by the components. The substrate of the carrier acts as a large heat sink to dissipate power generated by the components.

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Redwood City, CA, United States of America

Clinton C Chao