Deca Technologies Usa, Inc.

Clifford Sandstrom

Timothy Lee Olson

Craig Bishop

Robin Davis

Paul R Hoffman

Benedict San Jose

A method and related structure for a encapsulant defined land grid array (LGA) may comprise a semiconductor chip comprising conductive studs disposed over an active layer of the semiconductor chip, and a first encapsulant disposed around at least a portion of sidewalls of the conductive studs. A surface of the first encapsulant and conductive studs may be planarized. Conductive traces may be disposed over the encapsulant and coupled with the conductive studs. A dielectric layer may be disposed adjacent the conductive traces. LGA pads may be coupled with the conductive traces. A second encapsulant may be disposed over the dielectric layer and the LGA pads. A planar surface may be formed comprising the second encapsulant around the LGA pads and attachment areas on or over the LGA pads. The plurality of attachment areas may be coplanar or recessed the planar surface.

Encapsulant-defined land grid array (LGA) package and method for making the same

A method of making a QFN, DEN, or SON package may comprise forming an embedded chip panel comprising a plurality of semiconductor chips embedded in encapsulant and separated by saw streets. A conductive layer may be formed over the embedded chip panel, the conductive layer comprising bussing lines, contact pads, traces, and tie bars, wherein the bussing lines and tie bars extend into the saw streets. Vertical conductive elements may be disposed over and coupled with the conductive layer. An encapsulant layer may be disposed over the conductive layer and around the vertical conductive elements, wherein the vertical conductive elements comprise exposed ends and at least a portion of the tie bars is exposed from the encapsulant layer. Land pads, a conductive pad finish, or SMS may be electroplated over the vertical conductive elements by providing a current through the bussing lines and tie bars.

Quad flat no-lead (QFN) package with tie bars and direct contact interconnect build-up structure and method for making the same

A method of making a semiconductor device may include providing a large semiconductor die comprising conductive interconnects with a first encapsulant disposed over four side surfaces of the large semiconductor die, over the active surface of the large semiconductor die, and around the conductive interconnects. A first build-up interconnect structure may be formed over the large semiconductor die and over the first encapsulant. Vertical conductive interconnects may be formed over the first build-up interconnect structure and around an embedded device mount site. An embedded device comprising through silicon vias (TSVs) may be disposed over the embedded device mount site. A second encapsulant may be disposed over the build-up structure, and around at least five sides of the embedded device. A second build-up structure may be formed disposed over the planar surface and configured to be electrically coupled to the TSVs of the embedded device and the vertical conductive interconnects.

Fully molded semiconductor structure with through silicon via (TSV) vertical interconnects

An electronic assembly component may comprise at least one fan-out device comprising a first encapsulant disposed around a memory device or function and a processor device or function, and a fan-out interconnect structure disposed over the first encapsulant and the at least one fan-out device. Input output pads may be disposed over the fan-out interconnect structure. A structural support may comprise electrical routing and structural support pads, the structural support further comprising at least one mounting site to which the at least one fan-out device is coupled. An electrical connector may be configured to electrically couple the input output pads of the at least one fan-out device to the structural support pads. A second encapsulant may be disposed over at least a portion of the at least one fan-out device and the structural support.

Multi-chip or multi-chiplet fan-out device for laminate and leadframe packages

A semiconductor device may comprise a bridge die comprising copper studs. Copper posts may be disposed in a periphery of the bridge die. An encapsulant may be disposed on five sides of the bridge die, on sides of the copper studs, and on sides of the copper posts that leave ends of the copper studs and opposing first and second ends of the copper posts exposed from the encapsulant. A frontside build-up interconnect structure may be formed over the copper studs of the bridge die and coupled to second ends of the copper posts opposite the first ends of the copper posts. The frontside build-up interconnect structure comprising first pads at a first pitch within a footprint of the bridge die and second pads at a second pitch outside a footprint of the bridge die. The first pitch may be at least 1.5 times less than the second pitch.

Fully molded bridge interposer and method of making the same

The disclosure concerns devices and methods of forming an electronic assembly or semiconductor assembly, such as fully molded structures, comprising at least two components of a same or differing heights, which may further comprise a backside conductive material. The backside conductive material may be a good thermal conductor, a good electrical conductor, or both.

Fully molded structure with multi-height components comprising backside conductive material and method for making the same

An electronic assembly may include a component comprising conductive studs disposed over an active layer of the component. A first encapsulant layer may be disposed around four side surfaces of the component, over the active layer of the component, and contacting at least a portion of the sides of the conductive studs. A substantially planar surface may be disposed over the active layer of the component, wherein the substantially planar surface comprises ends of the conductive studs and the first encapsulant layer. The first encapsulant layer comprises a roughness less than 500 nanometers. First conductive elements may be disposed over the encapsulant and coupled with the conductive studs. A second layer of encapsulant may be disposed over the first conductive elements.

Molded direct contact interconnect structure without capture pads and method for the same

A semiconductor device may include an embedded device comprising through silicon vias (TSVs) extending from a first surface to a second surface opposite the first surface, wherein the embedded device comprises an active device, a semiconductor die comprising an active surface formed at the first surface, an integrated passive device (IPD), or a passive device. Encapsulant may be disposed over at least five sides of the embedded device. A first electrical interconnect structure may be coupled to a first end of the TSV at the first surface of the embedded device, and a second electrical interconnect structure may be coupled to a second end of the TSV at the second surface of the embedded device. A semiconductor die (e.g. a system on chip (SoC), memory device, microprocessor, graphics processor, or analog device), may be mounted over the first electrical interconnect of the TSV.

Stackable fully molded semiconductor structure with through silicon via (TSV) vertical interconnects and method of making the same

A method and related structure for a quad flat no-lead (QFN), dual flat no-lead (DFN) or small outline no-lead (SON) package without a leadframe. Disposing semiconductor chips face-up on a temporary carrier, disposing a first encapsulant layer around the semiconductor chip, the active layer and conductive stumps, forming a conductive layer and conductive contacts over the planar surface, disposing encapsulant over the first encapsulant layer, conductive layer and conductive contacts, forming a photoresist over the encapsulant with openings, forming conductive pads within the openings, forming a solderable metal system (SMS) or applying an organic solderability preservative (OSP) over the conductive pads, and cutting through the encapsulant around the chip to form the outline of a package.

Quad flat no-lead (QFN) package without leadframe and direct contact interconnect build-up structure and method for making the same

A multi-step conductive interconnect (MSI) may comprise a first step of the MSI comprising a first end and a second end opposite the first end, a first height (Ha) and a first diameter (Da). A second step of the MSI may comprise a first end and a second end opposite the first end. The first end of the second step contacts the second end of the first step. The second step may comprise a second height (Hb) and a second diameter (Db). The MSI may comprise a height (H) and a height to width aspect ratio (H:Da) greater than or equal to 1.5:1. A sidewall of the first step may comprise an offset (O) with respect to a sidewall of the second step to form a disjointed sidewall profile. The offset O may be in a range of 0.1 &#x3bc;m-20 &#x3bc;m.

Multi-step high aspect ratio vertical interconnect and method of making the same

Stackable fully molded semiconductor structure with through silicon via (TSV) vertical interconnects

A semiconductor device, and method of making the same, comprising a plurality of conductive studs formed over an active surface of a semiconductor die. The plurality of conductive studs may be disposed around a device mount site, wherein the device mount site comprises conductive interconnects comprising a height less than a height of the plurality of conductive studs. An encapsulant may be disposed around the semiconductor die and the conductive studs. A portion of the conductive studs may be exposed from the encapsulant at a planar surface. A build-up interconnect structure comprising one or more layers may be disposed over and coupled to the planar surface, the conductive studs, and the conductive interconnect. A device may be coupled to the conductive interconnects of the device mount site.

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Richfield, MN, United States of America

Clifford Sandstrom