Lsi Logic Corporation

Lsi Corporation

Clifford R Fishley

Abiola A Awujoola

Maurice O Othieno

Leonard Mora

Chok J Chia

Amar Amin

Michael L Lofstedt

Abiola Awujoola

Nael O Zohni

Maurice Othieno

An integrated circuit package includes a package substrate, a die attach pad formed on the package substrate for securing a die to the package substrate, a ground bonding ring formed on the package substrate for attaching core and I/O ground bond wires between the die and the package substrate, and a first plurality of bond fingers formed immediately adjacent to the ground bonding ring for attaching a first set of I/O signal bond wires between the package substrate and the die.

Wire bond integrated circuit package for high speed I/O

A die package generally including (A) ground paths routing a power ground from a ground power set of contact pads in a first conductive layer to a ground ring in a second conductive layer, (B) core paths routing a core voltage from a core power set of contact pads in the first conductive layer to a core ring in the second conductive layer, and (C) input/output voltage paths routing input/output voltages from an input/output power set of contact pads in the first conductive layer to an input/output ring in the second conductive layer, (i) the input/output ring surrounding the core ring, (ii) the ring being configured to power input and output circuits of the die, (iii) the input/output ring being split into ring segments isolated from each other and (iv) at least one particular ring segment having a length of less than a single connector pitch.

Ball grid array package layout supporting many voltage splits and flexible split locations

A carrier substrate includes an access region placed within the interior of the substrate that facilitates backside access to an integrated circuit die without damaging electrical integrity of the carrier substrate, a ring of die connection pads placed around the access region, and an array of package connection pads positioned around the perimeter of the top surface of the carrier substrate. In one embodiment, the perimeter depth of the array of package connections pads is selected to correspond to the number of electrical traces routable between minimally spaced package connection pads. The basic carrier substrate design is used to create an integrated circuit carrier family with each particular circuit carrier configured to receive a range of integrated circuit sizes and I/O counts such that each circuit carrier overlaps in size range with at least one other circuit carrier.

Integrated circuit carrier apparatus method and system

A heat spreader for use with an integrated circuit in a package, where the heat spreader is formed as a plate having a centrally disposed aperture with a diameter that is smaller than a minimum diameter of the integrated circuit. The heat spreader has an overall diameter that is no greater than a minimum diameter of the package. In this manner, the aperture in the heat spreader allows the plastic injected through a top gated mold form to pass through the heat spreader and more uniformly encapsulate the integrated circuit.

Top gated heat dissipation

A system and a method are provided for preventing damage to wafers arranged in a wafer cassette. In particular, an apparatus is provided to protect wafers arranged in a wafer cassette during insertion of a wafer into the cassette. In one embodiment, the apparatus may be a separate entity from the wafer cassette. In this manner, the apparatus may be situated about the cassette such that the wafers arranged in the cassette are protected during insertion of a wafer. In another embodiment, the wafer cassette itself may be adapted to partially cover and protect the wafers arranged in the cassette during insertion of a wafer. Consequently, a method is provided using either embodiment of the apparatus. In particular, the method may include inserting a wafer into a wafer cassette by shielding one or more slots of the cassette, exposing a designated slot of the cassette, and inserting a wafer into the designated slot.

Apparatus and method of semiconductor wafer protection

A configurable package for mounting an integrated circuit to a circuit board. The package has a substrate for receiving the integrated circuit. On the substrate are contacts for making electrical connections between the substrate and the integrated circuit. The substrate also has solder balls for making electrical connections between the substrate and the circuit board. Each one of the contacts is in electrical contact with one each of the solder balls. A clip ring/dam ring overlays and attaches to the substrate. The clip ring/dam ring forms a reservoir for receiving the integrated circuit on the substrate. Also, formed at the periphery of the clip ring/dam ring, are clamping tabs. The reservoir can be filled with an encapsulating material, such as epoxy, to complete the package. A lid is provided for covering the integrated circuit. A clip overlays the lid and releasably attaches to the clamping tabs of the insert, and retains the lid to the insert. The lid may have fins formed in it, to act as a heat sink, and dissipate heat by convection to air flowing within the environment.

Growing community of inventors

San Jose, CA, United States of America

Clifford R Fishley