Motorola Corporation

Clark Gilson Shepard

Alfred Larry Crouch

Matthew D Pressly

James G Gay

Grady L Giles

Bernard J Pappert

Daniel T Marquette

Michael Alan Mateja

Pamela S Laakso

Jason E Doege

Lee Allen Corley

Odis Dale Amason, Jr

Jennifer Lynn McKeown

Robert Ash

Multiple memory arrays (215, 225) in embedded applications are each tightly coupled to their own Built-In Self-Test (BIST) controller to form BISTed memory cells (210, 220) supporting structural and retention testing. Testing on multiple BISTed memories (210, 220) is initiated by common INVOKE (230), RETENTION (240), and RELEASE (250) signals. DONE and HOLD signals are combined (260, 280) from the multiple BISTed memories (210, 220) and delayed to generate a global 'all memory' DONE (265) and HOLD (285) signals. FAIL signals are combined (270) from the multiple BISTed memories (210, 220) to generate a global 'any memory' FAIL (275) signal. The BISTed memories can be combined in multiple stages to meet power limitations.

Multiple BIST controllers for testing multiple embedded memory arrays

A method of detecting defective CMOS devices by quiescent current (IDDQ) behavior using a monitor circuit resident in the expendable areas of a die and/or wafer. One embodiment of the present invention incorporates a monitor unit (10) into the scribe grid of a wafer, where pads (2, 3, 4) are built in the corners of the die (5) and connected to the monitor unit (10) via metal connects in the wafer. The monitor unit (10) determines defective die based on IDDQ as expressed by decay of voltage (Vdd) in time, where Vdd is supplied to a die by way of a switch (20) in the monitor unit (10). Alternate embodiments incorporate various configurations and incorporate functional and other tests into a wafer level test system. Other embodiments provide the monitor unit on the die, allowing for later testing and user confirmation.

Method and apparatus for performing operative testing on an integrated

A method and implementation for providing an improved testable design for an integrated circuit (IC) device. The integrated circuit includes a functional path for the implementation of a functional specification as well as a testing path for testing the timing specifications for the integrated circuit. Input switching devices are connected between input terminals of the IC and inputs to sequential circuit elements, for example flip-flop devices, in the IC. Similarly, output switching devices are connected between outputs of the flip-flop devices and output terminals of the IC. The switching devices are selectively operable to alternately connect the flip-flop devices into either a functional IC path for providing functional output signals during functional cycles, or into a testing IC path for providing testing output signals indicative of timing points throughout the IC during testing cycles. The IC is also operable to selectively disable tristate bus drivers during the testing cycles. The switching devices are arranged such that a single output terminal of the IC may be selectively used to provide both functional and testing output signals.

Scan based testing of an integrated circuit for compliance with timing

A data processor (10) has a single test controller (11). The test controller (11) has a test pattern generator portion (26) and a memory verification element (27). The test pattern generator (26) generates and communicates a plurality of test patterns to the plurality of memories (12, 13, and 14) through a second storage device (17). A first storage device (16) is used to store data read from the plurality of memories (12, 13, and 14). The data from the first storage device is selectively accessed by the memory verification element (27) via the bus (31). A bit (32) or more than one bit is used to communicate to external to the processor (10) whether the memories (12, 13, and 14) are operating in an error free manner.

Data Processor having a built-in internal self test controller for

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Austin, TX, United States of America

Clark Gilson Shepard