Applied Materials, Inc.

Cissy S Leung

David N Wang

Kenneth S Collins

Kam S Law

John M White

Dan Maydan

Ilya Perlov

Salvador P Umotoy

John A Adamik

Lawrence C Lei

Mei Yin Chang

Alfred W Mak

Kevin Lai

Sasson Roger Somekh

Ashok K Sinha

Steve G Ghanayem

Ping Jian

Thomas Wendling

Dennis Sauvage

Eric Andrew Englhardt

David K Cheng

Turgut Sahin

Dale R Dubois

Jerry Yuen Wong

Alan F Morrison

Manus K Wong

Sandy M Chew

Ching C Tang

Ron L Rose

David Nin-Kou Wang

Shane D Clark

A gate electrode connection structure formed by deposition of a tungsten nitride barrier layer and a tungsten plug, where the tungsten nitride and tungsten deposition are accomplished in situ in the same chemical vapor deposition (CVD) chamber. The tungsten nitride deposition is performed by plasma enhanced chemical vapor deposition (PECVD) using a plasma containing hydrogen, nitrogen and tungsten hexafluoride. Before deposition the wafer is pretreated with a hydrogen plasma to improve adhesion. The tungsten deposition process may be done by CVD using tungsten hexafluoride and hydrogen. A tungsten nucleation step is included in which a process gas including a tungsten hexafluoride, diborane and hydrogen are flowed into a deposition zone of a substrate processing chamber. Following the nucleation step, the diborane is shut off while the pressure level and other process parameters are maintained at conditions suitable for bulk deposition of tungsten.

Gate electrode connection structure by in situ chemical vapor deposition of tungsten and tungsten nitride

A multiple step chemical vapor deposition process for depositing a tungsten film on a substrate. A first step of the deposition process includes a nucleation step in which a process gas including a tungsten-containing source, a group III or V hydride and a reduction agent are flowed into a deposition zone of a substrate processing chamber while the deposition zone is maintained at or below a first pressure level. During this first deposition stage, other process variables are maintained at conditions suitable to deposit a first layer of the tungsten film over the substrate. Next, during a second deposition stage after the first stage, the flow of the group III or V hydride into the deposition zone is stopped, and afterwards, the pressure in the deposition zone is increased to a second pressure above the first pressure level and other process parameters are maintained at conditions suitable for depositing a second layer of the tungsten film on the substrate. In a preferred embodiment, the flow of the tungsten-containing source is stopped along with the flow of the group III or V hydride and after a period of between 5 and 30 seconds, the flow of the tungsten-containing source is restarted when the pressure is in the deposition zone is increased to the second pressure level.

Low resistivity W using B2H6 nucleation step

A high pressure, high throughput, single wafer, semiconductor processing reactor is disclosed which is capable of thermal CVD, plasma-enhanced CVD, plasma-assisted etchback, plasma self-cleaning, and deposition topography modification by sputtering, either separately or as part of in-situ multiple step processing. The reactor includes cooperating arrays of interdigitated susceptor and wafer support fingers which collectively remove the wafer from a robot transfer blade and position the wafer with variable, controlled, close parallel spacing between the wafer and the chamber gas inlet manifold, then return the wafer to the blade. A combined RF/gas feed-through device protects against process gas leaks and applies RF energy to the gas inlet manifold without internal breakdown or deposition of the gas. The gas inlet manifold is adapted for providing uniform gas flow over the wafer. Temperature-controlled internal and external manifold surfaces suppress condensation, premature reactions and decomposition and deposition on the external surfaces. The reactor also incorporates a uniform radial pumping gas system which enables uniform reactant gas flow across the wafer and directs purge gas flow downwardly and upwardly toward the periphery of the wafer for sweeping exhaust gases radially away from the wafer to prevent deposition outside the wafer and keep the chamber clean. The reactor provides uniform processing over a wide range of pressures including very high pressures. A low temperature CVD process for forming a highly conformal layer of silicon dioxide is also disclosed. The process uses very high chamber pressure and low temperature, the TEOS and ozone reactants. The low temperature CVD silicon dioxide deposition step is particularly useful for planarizing underlying stepped dielectric layers, either alone or in conjunction with a subsequent isotropic etch. A preferred in-situ multiple-step process for forming a planarized silicon dioxide layer uses (1) high rate silicon dioxide deposition at a low temperature and high pressure followed by (2) the deposition of the conformal silicon dioxide layer also at high pressure and low temperature, followed by (3) a high rate isotropic etch, preferably at low temperature and high pressure in the same reactor used for the two oxide deposition steps. Various combinations of the steps are disclosed for different applications, as is a preferred reactor self-cleaning step.

Thermal CVD/PECVD reactor and use for thermal chemical vapor deposition of silicon dioxide and in-situ multi-step planarized process

Method of forming gate electrode connection structure by in situ

Low resistivity W using B.sub.2 H.sub.6 nucleation step

A method for protecting a selected area of a substrate against deposition on the selected area. The method includes the steps of flowing a process gas into a substrate processing chamber and flowing a purge gas to the selected area of the substrate to prevent the process gas from contacting the selected area or minimize contact between the process gas and the selected area. In various embodiments the selected area is a backside periphery of the substrate or the edge of the substrate. Also in these embodiments, the process gas is flowed into a deposition zone in order to deposit a thin film layer over an upper surface of the substrate, and a flow of the process and purge gas is established such that the process gas flows radically across the upper surface of the substrate, combines with the purge gas near an edge of the substrate and exits the processing chamber through an exhaust system.

Method for protecting against deposition on a selected region of a

A apparatus for removing deposits from within a space at least partially delimited by a surface which is subject to attack from a plasma including a surface cover comprising a material which is inert to the plasma.

Plasma-inert cover and plasma cleaning process and apparatus employing

A substrate processing reactor capable of thermal CVD, plasma-enhanced CVD, plasma-assisted etchback, plasma self-cleaning and other substrate processing operations all of which can either be performed separately or as part of in-situ multiple step processing. The reactor incorporates a uniform radial gas pumping system which enables uniform reactant gas flow across the wafer. Also included are upper and lower purge gas dispersers. The upper purge gas disperser directs purge gas flow downwardly toward the periphery of the wafer while the lower gas disperser directs purge gas across the backside of the wafer. The radial pumping gas system and purge gas dispersers sweep radially away from the wafer to prevent deposition external to the wafer and keep the chamber clean.

Apparatus for preventing deposition gases from contacting a selected

A process for removing deposits from within a space at least partially delimited by a surface which is subject to attack from a plasma includes the steps of placing on the surface a cover comprising a material which is inert to the plasma, and then removing the deposits.

Plasma-inert cover and plasma cleaning process

A substrate processing apparatus comprising a housing defining a processing chamber for receiving a substrate therein. Inside the chamber a substrate supporting susceptor, including an upper substrate receiving portion is located. The receiving portion defines a walled pocket dimensioned to receive the substrate therein. When the substrate is so received the walls of the pocket define an annulus with the outer edge of the substrate. Typically the pocket walls are perpendicular to a primary plane of the substrate and are at least as high, and preferably twice as high, as the substrate is thick. At the outer, circumferential edge of the pocket a gas manifold is formed. The manifold is arranged so that, during processing, a gas which can be projected toward the edge of a substrate received in the pocket. This gas moves upwards between the annulus defined between the wall of the pocket and the outer edge of the substrate, thereby preventing processing gas from contacting the edge portion of the substrate.

Controlling edge deposition on semiconductor substrates

A substrate processing apparatus for processing a substrate having a peripheral edge, an upper surface for processing and a lower surface lying on a support. The apparatus includes a processing chamber which houses the substrate support, in the form of a heater pedestal including a substrate receiving surface for receiving the lower surface of the substrate. A circumscribing shadow ring is located around the pedestal to cover peripheral edge portion of the substrate. The shadow ring also defines a cavity, between itself and the pedestal, at the peripheral edge of the substrate. In operation, the chamber receives processing gas at a first pressure and purge gas is introduced into the cavity, between the ring and the pedestal, at a second pressure which is greater than the first pressure. Fluid conduits are provided to enhance the flow of the purge gas away from the peripheral edge of the substrate.

Reducing backside deposition in a substrate processing apparatus through

A bottom purge manifold for the gas purge channel of a CVD semiconductor processing chamber provides an obstruction in the purge gas flow from a purge gas passage to the central portion of the processing chamber. The gas flow is restricted by a ring having generally equally spaced holes therethrough obstructing the purge channel opening and retained in the channel by spring loaded retaining flanges. A set of fan-shaped slots carry the purge gas from the openings and direct it towards the center portion of the processing chamber. This manifold produces a generally uniform flow from the gas purge manifold to improve the uniformity of vapor deposition on the wafer's surface.

Bottom purge manifold for CVD tungsten process

A plasma processing apparatus has a chamber with an open top and a cover plate extending across the open top of the chamber. The cover plate has an opening therethrough. An annular shield of an electrical insulating material is secured to the cover plate around the opening and extends partially across the opening. An aluminum showerhead is within the shield and has holes therethrough through which a gas can pass into the chamber. The showerhead is connected to a source of RF voltage to provide a flow of RF power between the showerhead and an electrode within the chamber. The shield has a plurality of openings therethrough which allows the RF power to flow through the openings from the showerhead to the electrode in the event that the showerhead becomes coated with particles of an insulating material.

Plasma processing apparatus

A high pressure, high throughput, single wafer, semiconductor processing reactor is disclosed which is capable of thermal CVD, plasma-enhanced CVD, plasma-assisted etchback, plasma self-cleaning, and deposition topography modification by sputtering, either separately or as part of in-situ multiple step processing. The reactor includes cooperating arrays of interdigitated susceptor and wafer support fingers which collectively remove the wafer from a robot transfer blade and position the wafer with variable, controlled, close parallel spacing between the wafer and the chamber gas inlet manifold, then return the wafer to the blade. A combined RF/gas feed-through device protects against process gas leaks and applies RF energy to the gas inlet manifold without internal breakdown or deposition of the gas. The gas inlet manifold is adapted for providing uniform gas flow over the wafer. Temperature-controlled internal and external manifold surfaces suppress condensation, premature reactions and decomposition and deposition on the external surfaces. The reactor also incorporates a uniform radial pumping gas system which enables uniform reactant gas flow across the wafer and directs purge gas flow downwardly and upwardly toward the periphery of the wafer for sweeping exhaust gases radially away from the wafer to prevent deposition outside the wafer and keep the chamber clean. The reactor provides uniform processing over a wide range of pressures including very high pressures. A low temperature CVD process for forming a highly conformal layer of silicon dioxide is also disclosed. The process uses very high chamber pressure and low temperature, and TEOS and ozone reactants. The low temperature CVD silicon dioxide deposition step is particularly useful for planarizing underlying stepped dielectric layers, either alone or in conjunction with a subsequent isotropic etch. A preferred in-situ multiple-step process for forming a planarized silicon dioxide layer uses (1) high rate silicon dioxide deposition at a low temperature and high pressure followed by (2) the deposition of the conformal silicon dioxide layer also at high pressure and low temperature, followed by (3) a high rate isotropic etch, preferably at low temperature and high pressure in the same reactor used for the two oxide deposition steps. Various combinations of the steps are disclosed for different applications, as is a preferred reactor self-cleaning step.

Plasma-enhanced CVD process using TEOS for depositing silicon oxide

A high pressure, high throughout, single wafer semiconductor processing reactor is disclosed which is capable of thermal CVD, plasma-enhanced CVD, plasma-assisted etchback, plasma self-cleaning and deposition topography modification by sputtering, either separately or as part of in-situ multiple step processing. The reactor provides uniform processing over a wide range of pressures including very high pressures. A low temperature process for forming a highly conformal layer of silicon dioxide from a plasma of TEOS, oxygen and ozone is also disclosed. This layer can be planarized using an etchback process. Silicon oxide deposition and etchback can be carried out sequentially in the reactor.

Growing community of inventors

Fremont, CA, United States of America

Cissy S Leung