Hitachi, Ltd.

Nippon Hoso' Kyokai

Chushirou Kusano

Yukio Takasaki

Susumu Takahashi

Tomonori Tanoue

Tadaaki Hirai

Yoshinori Imamura

Sachio Ishioka

Hirofumi Ogawa

Tatsuo Makishima

Katsuhiko Mitani

Hiroshi Masuda

Kazuhiro Mochizuki

Keiichi Shidara

Yasuhiko Nonaka

Kenkichi Tanioka

Tsuyoshi Uda

Iwao Takemoto

Toshihisa Tsukada

Toshiyuki Akiyama

Toru Baji

Shigeru Shimada

Fumio Murai

Shinya Ohba

Eiichi Maruyama

Norio Koike

Haruo Matsumaru

Shinichiro Takatani

Masayoshi Saito

Naohiro Goto

Yasuharu Shimomoto

Eisuke Inoue

Hiroshi Mizuta

Tatsuro Kawamura

Shigeo Goto

Takeshi Kikawa

Masahiko Kawata

Eikyu Hiruma

Masatoshi Nakazawa

Hiroshi Miyazaki

Yohitsumu Ikeda

Teruo Uchida

A semiconductor device comprises a semiconductor substrate formed by a first single crystalline semiconductor material and semiconductor layers formed on the semiconductor substrate by a second single crystalline semiconductor material doped with an element which can easily surface segregate. The surface of the semiconductor substrate is formed of a crystalline plane substantially equivalent to a facet plane which is formed on the surface of the second single crystalline semiconductor material if the second single crystalline semiconductor material is epitaxially grown with being doped with the element on a (100) plane of the first single crystalline semiconductor material.

Semiconductor device

A compound semiconductor is etched by a step of substituting a composite element of a compound semiconductor with other element, thereby forming a compound layer on the surface of the compound semiconductor and a step of removing the compound layer from the surface. Etching depth is controlled not by etching time, but by the number of runs (repetitions) of the etching step, and thus can be precisely controlled.

Method and apparatus for etching compound semiconductor

A complementary semiconductor device is disclosed having a substrate and a four layer structure of pnpn provided on the substrate wherein the first three layers constitute a pnp-type bipolar transistor and the second to the fourth layer constitute an npn-type bipolar transistor. According to the present invention, the pnp- and npn-type transistor which are disposed on different portions of a principal surface of the substrate, respectively, can be produced concurrently by crystal growth and thus production steps are simple and yield is remarkably improved.

A method for fabricating a semiconductor device comprises the steps of forming the first semiconductor layer on a semiconductor substrate, forming a surface protection layer of antimony (Sb) or the material having Sb as its main component, executing the other steps necessary for the fabrication of the semiconductor device, removing the surface protection layer, and forming, on the first semiconductor layer thus exposed, the second semiconductor layer.

Method of fabricating semiconductor device using an Sb protection layer

A resonant tunneling device includes a superlattice layer which includes an interlaminated structure of three semiconductor layers each having a narrow energy bandgap and serving as a quantum well layer and four semiconductor layers each having a wide energy bandgap and serving as a barrier layer and in which three quantum levels are formed in the quantum well layers. A resonant tunneling phenomenon produced between the quantum levels provides peak current values which are substantially equal to each other, peak voltages which can be set independently from each other, and peak-to-valley (P/V) ratios which are high, thereby realizing a resonant tunneling device which has an excellent performance as a three state logic element for a logic circuit. By increasing the number of quantum well layers and the number of barrier layers, a logic element of four or more states can be realized for a logic circuit.

Resonant tunneling device

Microfabrication and large scale integration of a device can be realized by using a planar heterojunction bipolar transistor formed by a process comprising successively growing semiconductor layers serving as a subcollector, a collector, a base, and an emitter, respectively, through epitaxial growth on a compound semiconductor substrate in such a manner that at least one of the emitter junction and collector junction is a heterojunction, wherein a collector drawing-out metal layer is formed by the selective CVD method.

Process for fabricating heterojunction bipolar transistors

A high velocity electron beam scanning negatively charge biased image pickup tube has a target which includes at least a transparent conductive layer, a photoconductor layer and a layer for secondary electron emission on a light-transmissive insulating substrate, and in which the transparent conductive layer is arranged on a light incidence side, the photoconductor layer being made of amorphous silicon.

Image pickup tube

A photosensor including a transparent electrode for transmitting incident light and a photoconductive layer receiving light from the transparent electrode for performing photoelectric conversion, is disclosed in which the photoconductive layer is made of amorphous silicon, the amorphous silicon contains 5 to 30 atomic percent hydrogen and is doped with at least one selected from elements belonging to the groups II and III in such a manner that a region remote from the transparent electrode is higher in the concentration of the selected element than another region proximate to the transparent electrode, and a voltage is applied across the photoconductive layer so that a surface of the photoconductive layer facing the transparent electrode is at a positive potential with respect to another surface of the photoconductive layer opposite to the surface facing the transparent electrode.

Photosensor having impurity concentration gradient

An image pick-up tube has a photoelectric conversion target including a transparent substrate, and a transparent electrode and a photoconductive layer formed on the transparent substrate. An electron beam is scanned on the photoelectric conversion target. A first electrode is formed on a beam scanning surface of the photoconductive layer so as to be segmented in stripe or grid with its electrode segments electrically connected to each other. A second electrode is formed on the first electrode through an insulating layer with its electrode segments electrically connected to each other. An insulating layer may be interposed between the first electrode and the photoconductive layer.

Image pick-up tube having collector and balance electrodes

An image pickup tube of high velocity electron beam scanning and negatively charging system having a target including, on a transparent substrate, at least a transparent conductive film, a photoconductive layer, a layer for emitting secondary electrons, and stripe electrodes. The transparent substrate may be made of amorphous silicon.

Photoelectric conversion apparatus

A photoconductive film comprising a photo-conductive layer which is mainly made of selenium and a region added with tellurium in a direction of the thickness of the layer, wherein at least either one of a portion in a direction of hole flow of said region added with tellurium and a portion in the hole flow of another region which is located adjacent to said region added with tellurium is doped with at least one member selected from the group consisting of an oxide, a fluoride and elements which belong to the group II, III and VII, which are capable of forming a negative space charge in selenium, at a concentration in a range of 10 ppm to 1% by weight on an average. Typical examples of such oxide, fluoride and element include CuO, In.sub.2 O.sub.3, SeO.sub.2, V.sub.2 O.sub.5, MoO.sub.3, WO.sub.3, GaF.sub.2 InF.sub.3, Zn, Ga, In, Cl, I, Br and the like. The after image characteristic ascribable to incident light of high intensity can be significantly improved.

Doped photoconductive film comprising selenium and tellurium

A solid state image pickup device having a plurality of solid state elements in a two-dimensional array so as to form picture cells. Each solid state element includes a photoelectric converting element and a switching field effect transistor to permit scanning of the elements by scanners. To counteract noise and blooming, a second field effect transistor acting as an amplifier is connected between the photoelectric converting element and the switching field effect transistor. A third field effect transistor is coupled to the photoelectric converting element for resetting the same.

Solid state image pickup device

A photoconductive target having an electrode and a P-type conductive layer mainly made of Se and making rectifying contact at an interface with the electrode, with at least Te being doped in a portion of the P-type conductive layer. At least one metal fluoride forming shallow levels is doped in the region where the signal current is generated for the most part of the P-type conductive layer with an average concentration of not less than 50 ppm and not more than 5% by weight. The metal fluoride is preferably at least one selected from the group consisting of LiF, NaF, MgF.sub.2, CaF.sub.2, BaF.sub.2, AlF.sub.3, CrF.sub.3, MnF.sub.2, CoF.sub.2, PbF.sub.2, CeF.sub.3 and TlF. The high light sticking of the photoconductive target can thus be considerably reduced.

Photoconductive target

Growing community of inventors

Tokorozawa, Japan

Chushirou Kusano