Audi Ag

Abb Schweiz Ag

Hitachi Energy Ltd

Hitachi Energy Switzerland Ag

Abb Power Grids Switzerland Ag

Chunlei Liu

Fabian Mohn

Munaf Rahimo

Peter Karl Steimer

Jürgen Schuderer

Franziska Brem

Franc Dugal

Francisco Canales

Uwe Drofenik

Slavo Kicin

Juergen Schuderer

Gernot Riedel

Alexey Sokolov

Joonas Puukko

An electrical contact arrangement electrically contacts at least two power semiconductor devices, and comprises at least two bond wires and at least three electrical contacts, comprising an alternating current contact, a positive direct current contact, and a negative direct current contact. Each electrical contact comprises a ground potential part; contact part; and insulation part on the ground potential part. The contact part is provided on the insulation part. At least two electrical contacts are separated by a gap between the insulation parts and the gap between the contact parts of the separated electrical contacts. A bond wire connects a first power semiconductor device on a contact part of the positive direct current contact with a contact part of the alternating current contact. A bond wire connects a second power semiconductor device on the contact part of the alternating current contact with a contact part of the negative direct current contact.

Electrical contact arrangement, power semiconductor module, method for manufacturing an electrical contact arrangement and method for manufacturing a power semiconductor module

In one embodiment, a power module device includes a base plate, an electrically insulating ceramic layer on the base plate, and an electrically insulating first insulating layer on the ceramic layer. The first insulating layer includes a prepreg material. An electrically conductive lead frame is disposed on the first insulating layer and electrically insulated therefrom. A power semiconductor device disposed on the lead frame and embedded between the lead frame and a second insulating layer.

Power module device with an embedded power semiconductor device

A power semiconductor module includes a substrate with a metallization layer and a power semiconductor chip bonded to the metallization layer of the substrate. A metallic plate has a first surface bonded to a surface of the power semiconductor chip opposite to the substrate. The metallic plate has a central part and a border that are both bonded to the power semiconductor chip. The border of the metallic plate is structured in such a way that the metallic plate has less metal material per volume at the border as compared to the central part of the metallic plate. Metallic interconnection elements are bonded to a second surface of the metallic plate at the central part.

Power semiconductor package with highly reliable chip topside

A method for producing a semiconductor module, involving the steps: providing a carrier plate and a substrate having a bonding layer arranged on a surface of the carrier plate or the substrate, applying adhesive in multiple adhesive areas of the carrier plate or the substrate which are free from the bonding layer, positioning the substrate on the carrier plate such that the substrate and the carrier plate are in contact with the bonding layer and the adhesive, and joining the substrate and the carrier plate across the bonding layer by melting or sintering of the bonding layer.

Method for producing a semiconductor module by using adhesive attachment prior to sintering

A semi-manufactured power semiconductor module includes a substrate for bonding at least one power semiconductor chip; a first leadframe bonded to the substrate and providing power terminals; and a second leadframe bonded to the substrate and providing auxiliary terminals; wherein the first leadframe and/or the second leadframe include an interlocking element adapted for aligning the first leadframe and the second leadframe with respect to each other and/or with respect to a mold for molding an encapsulation around the substrate, the first leadframe and the second leadframe.

Manufacturing of a power semiconductor module

A power semiconductor device includes a Si chip providing a Si switch and a wide bandgap material chip providing a wide bandgap material switch, wherein the Si switch and the wide bandgap material switch are electrically connected in parallel. A method for controlling a power semiconductor device includes: during a normal operation mode, controlling at least the wide bandgap material switch for switching a current through the power semiconductor device by applying corresponding gate signals to at least the wide bandgap material switch; sensing a failure in the power semiconductor device; and, in the case of a sensed failure, controlling the Si switch by applying a gate signal, such that a current is generated in the Si chip heating the Si chip to a temperature forming a permanent conducting path through the Si chip.

Power semiconductor device with active short circuit failure mode

A power semiconductor device includes a base plate; a Si chip including a Si substrate, the Si chip attached to the base plate; a first metal preform pressed with a first press pin against the Si chip; a wide bandgap material chip comprising a wide bandgap substrate and a semiconductor switch provided in the wide bandgap substrate, the wide bandgap material chip attached to the base plate; and a second metal preform pressed with a second press pin against the wide bandgap material chip; the Si chip and the wide bandgap material chip are connected in parallel via the base plate and via the first press pin and the second press pin; the first metal preform is adapted for forming a conducting path through the Si chip, when heated by an overcurrent; and the second metal preform is adapted for forming an temporary conducting path through the wide bandgap material chip or an open circuit, when heated by an overcurrent.

Power semiconductor module with short circuit failure mode

A power module included a plurality of normally-on semiconductor switches based on a wide bandgap substrate, the normally-on semiconductor switches connected in parallel; and a balancing unit including a capacitor and a balancing semiconductor switch connected in series, which are connected in parallel to the normally-on semiconductor switches.

Growing community of inventors

Oberrohrdorf, Switzerland

Chunlei Liu