Taiwan Semiconductor Manufacturing Comp. Ltd.

Chung-Yu Wang

Pei-Haw Tsao

Chender Huang

Ken Hui Chen

Chen-Shien Chen

Szu-Wei Lu

Mirng-Ji Lii

Kuo-Chin Chang

Clinton Chao

Chih-Chiang Chen

Han-Liang Tseng

Hank Huang

A light-emitting device (LED) package component includes an LED chip having a first active bond pad and a second active bond pad. A carrier chip is bonded onto the LED chip through flip-chip bonding. The carrier chip includes a first active through-substrate via (TSV) and a second active TSV connected to the first and the second active bond pads, respectively. The carrier chip further includes a dummy TSV therein, which is electrically coupled to the first active bond pad, and is configured not to conduct any current when a current flows through the LED chip.

LED flip-chip package structure with dummy bumps

A method for fabricating a semiconductor package is provided. In one embodiment, a semiconductor chip having a plurality of exposed conductive layers thereon is provided. A first substrate having a first surface and a second surface is provided, the first surface having a plurality of exposed via plugs thereunder. The semiconductor chip is bonded to the first substrate, wherein the plurality of exposed conductor layers are aligned and in contact with the surfaces of the exposed via plugs. A portion of the second surface of the first substrate is then removed to expose the opposite ends of the plurality of via plugs. A plurality of UBM layers is formed on the surfaces of the opposite ends of the plurality of via plugs. A plurality of solder bumps is formed and mounted on the UBM layers. A second substrate having a first surface and a second surface is provided, the solder bumps being mounted to the first surface of the second substrate. A plurality of solder balls is formed and mounted to the second surface of the second substrate. A third substrate is mounted to the solder balls.

Method for fabricating a semiconductor package including stress relieving layer for flip chip packaging

A matrix form semiconductor package substrate that has an electrode situated in-between a plurality of IC package substrates for providing electrical communication to conductive pads on the substrate is provided. The matrix form semiconductor package substrate includes a plurality of IC package substrates that are integrally formed on a strip in a matrix pattern that has a boundary between each two of the plurality of IC package substrates. Each of the plurality of IC package substrates has a multiplicity of conductive pad traces and an electrode, or a plating bar, formed in a serpentine configuration along the boundary for providing electrical communication to the multiplicity of conductive pads.

Matrix form semiconductor package substrate having an electrode of serpentine shape

Methods for forming solder bumps on a semiconductor device are provided. In one embodiment, a substrate is provided having at least one contact pad formed thereon. A passivation layer is formed overlying the substrate, the passivation layer having at least one opening therein exposing a portion of the contact pad. A UBM (Under Bump Metallurgy) layer is formed overlying the passivation layer and the contact pad. A patterned and etched light sensitive layer is provided overlying the UBM layer, the light sensitive layer defining at least one opening therein. A sidewall bump layer is formed over the exposed surfaces of the light sensitive layer and the UBM layer. A portion of the sidewall bump layer above the light sensitive layer is removed. A solder material is deposited in the opening bordered by the etched sidewall bump layer to form a solder column. The solder column is then reflown to create a solder bump.

Method to increase bump height and achieve robust bump structure

A microelectronic assembly, and method of making the same, including a wire stitch bonded on an electroplated gold bump or electroless nickel/gold bump on a bond pad of an integrated circuit chip. The electroplated gold bump or electroless nickel/gold bump provides a relatively flat upper surface which is excellent for making a wire stitch bond thereto. The microelectronic assembly may include a multiple integrated circuit chip stack attached to a substrate such as a ball grid array. The electroplated gold bumps or electroless nickel/gold bumps may be formed on all of the integrated circuit chips and wire stitch bonds formed on the electroplated gold bumps or electroless nickel/gold bumps thereby connecting the integrated circuit chips to each other or to an underlying ball grid array.

Wire stitch bond on an integrated circuit bond pad and method of making the same

A method for protecting a passivation layer during a solder bump formation process including providing a semiconductor process wafer having a process surface including at least two metal layers comprising an uppermost metal layer and a lowermost metal layer said lowermost metal layer overlying a passivation layer including metal bonding pad regions; photolithographically patterning and anisotropically etching through a first thickness portion of at least the uppermost metal layer to form a first patterned metal layer portion disposed over the metal bonding pad regions and reveal a second thickness portion including the lowermost metal layer; forming a solder bump over the first patterned metal layer portion according to at least a first reflow process; and, anisotropically etching through the second thickness portion surrounding the completely formed solder bump to reveal the passivation layer.

Method of protecting a passivation layer during solder bump formation

A method of improving adhesion of a surface including the following steps. A structure having an upper surface is provided. A composite anchor layer is formed over the upper surface of the structure. The composite anchor layer including at least an upper anchor sub-layer and a lower anchor sub-layer. The upper anchor sub-layer is patterned to form a dense pattern of upper sub-anchors. The lower anchor sub-layer is then patterned using the upper sub-anchors as masks to form lower sub-anchors. The respective upper sub-anchors and lower sub-anchors form a dense pattern of anchors whereby the dense pattern of anchors over the upper surface improve the adhesion of the surface.

Growing community of inventors

Hsin-Chu, Taiwan

Chung-Yu Wang