Elite Semiconductor Memory Technology, Inc

Mosaid Technologies Corporation

Conversant Intellectual Property Management Incorporated

Seoul National University

Chung-Shan Kuo

Chung-Zen Chen

Yang-Chieh Lin

Chih-Hao Chen

A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal.

Method for erasing memory cells in a flash memory device using a positive well bias voltage and a negative word line voltage

A method for programming memory cells of a selected word line has steps of: providing a first word line programming signal being at plurality of voltage levels in different programming slots of a current programming operation to the memory cells of the selected word line, wherein the first word line programming signal is a ramping voltage signal; and providing a second line programming signal being at plurality of voltage levels in different programming slots of a next programming operation to the memory cells of the selected word line, wherein the second word line programming signal is another one ramping voltage signal; wherein the highest voltage levels of the first and second word line programming signals are identical to each other, and a number of the voltage levels of the first word line programming signal is larger than that of the second word line programming signal.

Method for programming selected memory cells in nonvolatile memory device and nonvolatile memory device thereof

A method of booting a system with a non-volatile memory device includes at least the following steps: when the system is powered on, reading a status flag of at least a memory block of the non-volatile memory device, wherein the status flag indicates whether an erase operation applied to the memory block is successfully completed; selectively performing a leakage calibration process upon the memory block according to the status flag; and booting the system according to a boot code stored in the non-volatile memory device.

Method of booting system having non-volatile memory device with erase checking and calibration mechanism and related memory device

A method of trimming a reference cell in a semiconductor memory device comprises the steps of: generating a reference current based on a bias voltage applied to the reference cell; generating a first current and a second current based on the value of a control voltage and the resistance of a precision resistor disposed outside the semiconductor memory device; comparing the reference current with the first current; comparing the reference current with the second current; programming the reference cell if the value of the reference current is greater than that of the first current; and erasing the reference cell if the value of the reference current is less than that of the second current. The value of the second current is less than that of the first current.

Apparatus and method for trimming reference cell in semiconductor memory device

Word line driver in a hierarchical NOR flash memory

A bit line precharge circuit is provided by the present invention. The bit line precharge circuit groups the precharge sub-circuits to share one drain bias controller. The drain bias controller has an inverter and a NMOS clamping transistor to form a negative feedback loop, to quickly precharge bit lines. When operating in read operation, only one drain bias controller is needed. Therefore, it can greatly save the layout area and operating power consumption without any extra dummy bit line or layout expansion.

Bit line precharge circuit

A charge pump circuit including a plurality of controlled charge pumps (CPs), a plurality of uncontrolled CPs, a plurality of control units, and an output unit is provided. Each controlled CP determines whether to provide charges to a node by a control signal, and each uncontrolled CP constantly provides charges to the node. The higher the node voltage at the node is, the more the controlled CPs not providing charge to the node are, so as to suppress the voltage of the node. In addition, the output unit regulates and outputs an output voltage according to the node voltage by the negative feedback.

Charge pump circuit

An erase method used in an array of flash memory cells arranged in a plurality of sectors provides each sector with an erase flag. The erase flag of sectors to be erased are set to a first value. The memory cells are sequentially verified from a first sector to a last sector whose flag is set to the first value and for each sector from a first address to a last address. When verification fails and the number of the same-cell-verifications is less than a predetermined number, the method applies an erase pulse and verifies the memory call at the same memory address again. When verification fails and the number of same-cell-verifications reaches the predetermined number, the remaining sectors whose flag is set to the first value are verified. When each memory cell of a sector to be erased passes verification, the erase flag of the sector is set to a second value. When the flag of each sector to be erased is set to the second value, the erase operation is terminated.

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Shulin, Taiwan

Chung-Shan Kuo