Fairchild Semiconductor Corporation

Semiconductor Components Industries, LLC

Chung-Lin Wu

Rajeev Dinkar Joshi

Maria Cristina Estacio

Oseob Jeon

Bigildis Dosdos

Jerome Teysseyre

Romel Nogas Manatad

Ahmad Ashrafzadeh

Eddy Tjhia

Daniel Marvin Kinzer

Steven Paul Sapp

Venkat Iyer

Maria Clemens Ypil Quinones

Maria Cristina B Estacio

James J Murphy

Michael D Gruenhagen

Suku Kim

Boon Huan Gooi

Mark Larsen

Erwin Ian Almagro

Yoonhwa Choi

Byoung-Ok Lee

Janusz Bryzek

Elsie Agdon Cabahug

Jonathan A Noquil

Etan Shacham

Justin N Chiang

David Chong

Suresh Belani

John R Constantino

Lay Yeap Lim

Timwah Luk

Seung Yong Choi

Douglas E Dolan

Vijay Ullal

Marie Clemens Ypil Quinones

Marlon Bartolo

Robert L Krause

Michael M Dube

Sunggeun Yoon

Shibaek Nam

Tan Teik Keng

Hamza Yilmaz

Qi Wang

Adrian Mikolajczak

Ihsiu Ho

Minhua Li

Rohit Dikshit

Bigidis Dosdos

In a general aspect, an electronic device assembly can include a dielectric substrate having a first surface and a second surface opposite the first surface and a leadframe including: a first leadframe portion including a first plurality of signal leads; and a second leadframe portion including a second plurality of signal leads. The substrate can be coupled with a subset of the first plurality of signal leads and a subset of the second plurality of signal leads. Signal leads of the first plurality of signal leads, other than the subset of the first plurality of signal leads, can be spaced from the dielectric substrate. Signal leads of the second plurality of signal leads, other than the subset of the second plurality of signal leads, can be spaced from the dielectric substrate. The assembly can further include one or more semiconductor die that are electrically coupled with the substrate and the leadframe portions.

Electronic device packaging with galvanic isolation

In a general aspect, an apparatus can include a leadframe including a plurality of leads disposed along a single edge of the apparatus. The apparatus can also include an assembly including a substrate and a plurality of semiconductor die disposed on the substrate, the assembly being mounted on the leadframe and an inductor having a first terminal and a second terminal. The first terminal of the inductor can be electrically coupled with the leadframe via a first contact pad of the leadframe. The second terminal of the inductor can be electrically coupled with the leadframe via a second contact pad of the leadframe. The first contact pad and the second contact pad can be exposed through a molding compound by respective mold cavities defined in the molding compound. The leadframe, the assembly and the inductor can be arranged in a stacked configuration.

Vertical and horizontal circuit assemblies

In one general aspect, a device can include a leadframe including at least one of an external input terminal or an external output terminal, an interposer made of an insulating material, and a redistribution layer coupled to the interposer and made of a conductive material. The redistribution layer can include a plurality of traces. The device can also include a semiconductor die disposed between the redistribution layer and the leadframe.

Substrate interposer on a leaderframe

In a general aspect, an apparatus can include a leadframe including a plurality of leads disposed along a single edge of the apparatus. The apparatus can also include an assembly including a substrate and a plurality of semiconductor die disposed on the substrate, the assembly being mounted on the leadframe and an inductor having a first terminal and a second terminal. The first terminal of the inductor can be electrically coupled with the leadframe via a first conductive clip, where the first terminal of the inductor can be coupled with a contact pad of the first conductive clip. The second terminal of the inductor can be electrically coupled with the leadframe via a second conductive clip, where the second terminal of the inductor can be coupled with a contact pad of the second conductive clip. The leadframe, the assembly and the inductor can be arranged in a stacked configuration.

In one general aspect, an apparatus can include a leadframe including a plurality of leads configured to provide electrical connections for the apparatus. The apparatus can also include a semiconductor die disposed on the leadframe and a conductive clip electrically coupling the semiconductor die with the leadframe. The apparatus can further include a heat slug disposed on the conductive clip. The heat slug can include a thermally conductive and electrically insulative material.

Semiconductor device assemblies

In a general aspect, an electronic device assembly can include a dielectric substrate having a first surface and a second surface opposite the first surface and a leadframe including: a first leadframe portion including a first plurality of signal leads; and a second leadframe portion including a second plurality of signal leads. The substrate can be coupled with a subset of the first plurality of signal leads and a subset of the second plurality of signal leads. Signal leads of the first plurality of signal leads, other than the subset of the first plurality of signal leads, can be spaced from the dielectric substrate. Signal leads of the second plurality of signal leads, other than the subset of the second plurality of signal leads, can be spaced from the dielectric substrate. The assembly can further include first and second semiconductor die that are electrically coupled with the substrate and the leadframe portions.

Substrate interposer on a leadframe

In some general aspects, an apparatus may include a first semiconductor die, a second semiconductor die, and a capacitive isolation circuit being coupled to the first semiconductor die and the second semiconductor die. The capacitive isolation circuit may be disposed outside of the first semiconductor die and the second semiconductor die. The first semiconductor die, the second semiconductor die, and the capacitive circuit may be included in a molding of a semiconductor package.

Isolation between semiconductor components

In a general aspect, an apparatus can include a leadframe including a plurality of leads configured to be coupled with a printed circuit board. The plurality of leads can be disposed along a single edge of the apparatus. The apparatus can also include an assembly including a substrate and a plurality of semiconductor die disposed on the substrate. The assembly can being mounted on the leadframe. The apparatus can further include an inductor having a first terminal and a second terminal. The first terminal of the inductor can being coupled with the leadframe via a first contact pad, and the second terminal of the inductor can be coupled with the leadframe via a second contact pad. The leadframe, the assembly and the inductor can be arranged in a stacked configuration.

In one general aspect, a package can include a semiconductor die having a first terminal on a first side of the semiconductor die and a second terminal on a second side of the semiconductor die, a leadframe portion electrically coupled to the second terminal of the semiconductor die, and a molding compound. The first terminal on the first side of the semiconductor die, a first surface of the leadframe portion, and a first surface of the molding compound can define at least a portion of a first surface of the package. A second surface of the molding compound and a second surface of the leadframe portion can define at least a portion of a second surface of the package parallel to the first surface of the package, and the second surface can be on an opposite side of the package from the first surface of the package.

Packaged semiconductor devices and methods of manufacturing

In one general aspect, a method can include forming a redistribution layer on a substrate using a first electroplating process, and forming a conductive pillar on the redistribution layer using a second electroplating process. The method can include coupling a semiconductor die to the redistribution layer, and can include forming a molding layer encapsulating at least a portion of the redistribution layer and at least a portion of the conductive pillar.

Package including a semiconductor die and a capacitive component

A first embodiment is a common drain+clip. It has a conventional drain contact on its bottom surface and is flip chip mounted on a half-etched leadframewhich has external source, gate and drain contacts connected to the sources, gate and common drain of the die. Common drain clipconnects the drainto external contacts between opposite gate contacts. A second embodiment is a direct drain embodiment+heatslug. The devicehas a top drain contactthat extends to the common drainacross the bottom of the die which is flip chip mounted to a half-etched leadframe having external source, gate and drain contacts connected to the sources, gates and common drain of the die

Common drain power clip for battery pack protection mosfet

Apparatus related to an improved package including a semiconductor die

Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.

Semiconductor die package and method for making the same

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San Jose, CA, United States of America

Chung-Lin Wu