Nan Ya Technology Corporation

Inotera Memories, Inc.

Chung-Lin Huang

Chi-Hui Lin

Ching-Nan Hsiao

Ying-Cheng Chuang

Tzung-Han Lee

Ron Fu Chu

Hung-Mine Tsai

Tzung Han Lee

Shin-Bin Huang

Cheng-Chih Huang

Shih-Yang Chiu

Hsien-Wen Liu

Pei-Ing Paul Lee

Chung-Peng Hao

Szu-Yao Chang

Ron-Fu Chu

Shin Bin Huang

Mao-Quan Chen

Chung-Yuan Lee

Ming-Cheng Chang

Hsu Chiang

Sheng-Tsung Chen

Yung-Meng Huang

Lai-Cheng Tien

Hung-Ming Tsai

Chih-Lin Huang

Cheng-Yeh Hsu

Zhi-Yi Huang

Chih-Hui Lin

Yih-Ren Shao

Chien-Hsun Chen

Hsi-Hua Chang

Chih-Hsiang Wu

Dah-Wei Liu

The present disclosure provides a memory device. The memory device includes a substrate, a first gate electrode arranged within the substrate, a second gate electrode arranged within the substrate and over the first gate electrode, and an electrical insulating structure separating the substrate, the first gate electrode and the second gate electrode from one another. The memory device further includes a first dielectric layer arranged within the substrate and covering an upper portion of the electrical insulating structure from a top-view perspective.

Memory cell with improved insulating structure

The present application provides a memory device having an ultra-lightly doped region and a manufacturing method of the memory device. The memory device includes a semiconductor substrate including a word line extending into the semiconductor substrate, wherein the semiconductor substrate is defined with a source region, a drain region and an ultra-lightly doped region under the drain region, the word line is disposed between the source region and the drain region, and the ultra-lightly doped region is disposed at a sidewall of the word line.

Memory device having ultra-lightly doped region

A semiconductor device structure and method for manufacturing the same are provided. The semiconductor device structure includes a first word line, a second word line, a gate dielectric structure, a channel layer, and a bit line. The first word line and second word line extend along a first direction. The gate dielectric structure is disposed on a first sidewall of the first word line and on a second sidewall of the second word line. The channel layer is disposed on a first sidewall of the gate dielectric structure. The bit line is disposed on the channel layer and extends along a second direction substantially perpendicular to the first direction. A first roughness of a first sidewall of the channel is different from a second roughness of a second sidewall of the channel layer.

Semiconductor device structure having a channel layer with different roughness

A manufacturing method of a semiconductor device includes forming an opening in a substrate, implanting a dopant in the substrate from a sidewall of the opening such that a doping region is formed in the substrate at the sidewall of the opening, filling a dielectric material in the opening to form a first dielectric structure after implanting the dopant in the substrate from the sidewall of the opening, and forming a passing word line in the dielectric structure.

Semiconductor device and manufacturing method thereof

A semiconductor device includes a substrate, a passing word line in the substrate, and a dielectric structure surrounding the passing word line. The dielectric structure has an enlargement portion at a bottom of the dielectric structure, and a maximum width of the enlargement portion of the dielectric structure is wider than a width of a top of the dielectric structure.

Semiconductor device with dielectric structure having enlargemant portion surrounding word line

A semiconductor device structure and method for manufacturing the same are provided. The method includes: providing a substrate; forming a first word line and a second word line extending along a first direction; forming a dielectric material conformally on a first sidewall of the first word line and on a second sidewall of the second word line, wherein the second sidewall of the second word line faces the first sidewall of the first word line; forming a semiconductor material on a sidewall of the dielectric material; and patterning the dielectric material and the semiconductor material to form a gate dielectric structure and a channel layer between the first word line and the second word line.

Method of manufacturing semiconductor device structure having a channel layer with different roughness

Manufacturing method of a semiconductor device using a protect layer along a top sidewall of a trench to widen the bottom of the trench

The present disclosure provides a method of manufacturing a semiconductor structure. The method includes providing a substrate defined with a peripheral region and an array area at least partially surrounded by the peripheral region; disposing an insulating layer over the substrate; disposing a capping layer over the insulating layer; disposing a hardmask stack on the capping layer; patterning the hardmask stack; removing portions of the capping layer exposed through the hardmask stack; removing portions of the insulating layer exposed through the hardmask stack; removing portions of the substrate exposed through the capping layer and the insulating layer to form a plurality of fins in the array area and a first elongated member at least partially surrounding the plurality of fins; removing the hardmask stack; and forming an isolation over the substrate and surrounding the plurality of fins and the first elongated member.

Method of manufacturing semiconductor structure having dummy pattern around array area

A method of forming a semiconductor structure includes following steps. A semiconductor material structure is formed over a substrate. A first pad layer is formed over the semiconductor material structure. The first pad layer and the semiconductor material structure are etched to form a trench. An oxidation process is performed on a sidewall of the semiconductor material structure to form a first oxide structure on the sidewall of the semiconductor material structure. A second oxide structure is formed in the trench.

Semiconductor structure and method of forming the same

The present disclosure provides a semiconductor structure and a method of manufacturing the semiconductor structure. The semiconductor structure includes a substrate defined with a peripheral region and an array area at least partially surrounded by the peripheral region, wherein the substrate includes a plurality of fins protruding from the substrate and disposed in the array area, and a first elongated member protruding from the substrate and at least partially surrounding the plurality of fins; an insulating layer disposed over the plurality of fins and the first elongated member; a capping layer disposed over the insulating layer; and an isolation surrounding the plurality of fins, the first elongated member, the insulating layer and the capping layer.

Semiconductor structure having dummy pattern around array area and method of manufacturing the same

An antifuse element includes a conductive region formed in a semiconductor substrate extending in a first direction, a dielectric layer formed on a portion of the conductive region, a first conductive plug formed on the dielectric layer, a second conductive plug formed on another portion of the conductive region, a first conductive member formed over the first conductive plug, and a second conductive member formed over the second conductive plug. The dielectric layer has a first dielectric portion extending in a second direction, and a second dielectric portion extending in the first direction, in which the dielectric layer implements an electrical isolation between the conductive region and the first conductive plug. The first conductive plug has a first region of a first width and a second region of a second width, and the first width is greater than the second width.

Antifuse element

The present disclosure provides a semiconductor capacitor structure. The semiconductor capacitor structure includes a substrate, a comb-like bottom electrode disposed over the substrate, a top electrode disposed over the comb-like bottom electrode, and a dielectric layer sandwiched between the top electrode and the comb-like bottom electrode. The comb-like bottom electrode includes a plurality of tooth portions parallel to the substrate and a supporting portion coupled to the plurality of tooth portions and perpendicular to the substrate.

Semiconductor capacitor structure

The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate, a semiconductor layer, and a contact. The semiconductor layer is over the semiconductor substrate. The contact has an interface with the semiconductor layer. The contact is substantially tapered toward the semiconductor substrate to the interface.

Semiconductor device and method of forming the same

The present disclosure provides a semiconductor structure and a method for manufacturing the semiconductor structure. The semiconductor structure includes a semiconductor substrate, a dielectric layer, a barrier layer, and a conductive layer. The semiconductor substrate has a plurality of mesas. The dielectric layer is disposed over the semiconductor substrate and has a plurality of blocks disposed over the mesas, respectively. The barrier layer is formed over a first lateral surface of the mesa, a second lateral surface of the block, an upper surface of the semiconductor substrate adjacent to the first lateral surface, and a front surface of the dielectric layer adjacent to the second lateral surface. The conductive layer has a base and a plurality of protrusions extending from the base and in contact with the barrier layer disposed over the upper surface, the first lateral surface, and the second lateral surface. A grain size of the base and the protrusions is consistent.

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Taichung, Taiwan

Chung-Lin Huang