Taiwan Semiconductor Manufacturing Comp. Ltd.

Chung-Hsing Chang

Chin-Hsiang Lin

Burn Jeng Lin

Sheng-Chi Chin

Chang-Ming Dai

Shih-Ming Chang

Wen-Chuan Wang

Chi-Lun Lu

Jan-Wen You

San-De Tzu

Chih-Cheng Chin

Chun-Kuang Chen

Jeng-Horng Chen

Chien-Hung Lin

Chia-Hui Lin

Fu-Jye Liang

Ming-Shuo Yen

Bang-Ching Ho

Chen-Hao Hsieh

Hsin-Chang Li

A hologram reticle and method of patterning a target. A layout pattern for an image to be transferred to a target is converted into a holographic representation of the image. A hologram reticle is manufactured that includes the holographic representation. The hologram reticle is then used to pattern the target. Three-dimensional patterns may be formed in a photoresist layer of the target in a single patterning step. These three-dimensional patterns may be filled to form three-dimensional structures or else used in a multi-surface imaging composition. The holographic representation of the image may also be transferred to a top photoresist layer of a top surface imaging (TSI) semiconductor device, either directly or using the hologram reticle. The top photoresist layer may then be used to pattern an underlying photoresist layer with the image. The lower photoresist layer is used to pattern a material layer of the device.

Holographic reticle and patterning method

A hologram reticle and method of patterning a target. A layout pattern for an image to be transferred to a target is converted into a holographic representation of the image. A hologram reticle is manufactured that includes the holographic representation. The hologram reticle is then used to pattern the target. Three-dimensional patterns may be formed in a photoresist layer of the target in a single patterning step. These three-dimensional patterns may be filled to form three-dimensional structures. The holographic representation of the image may also be transferred to a top photoresist layer of a top surface imaging (TSI) semiconductor device, either directly or using the hologram reticle. The top photoresist layer may then be used to pattern an underlying photoresist layer with the image. The lower photoresist layer is used to pattern a material layer of the device.

A process is described for shrinking gate lengths and poly interconnects simultaneously during the fabrication of an integrated circuit. A positive tone photoresist is coated on a substrate and is first exposed with an alternating phase shift mask that has full size scattering bars which enable a gate dimension to be printed that is &#xbc; to &#xbd; the size of the exposing wavelength. The substrate is then exposed using a tritone attenuated phase shift mask with a chrome blocking area to protect the shrunken gates and attenuated areas with scattering bars for shrinking the interconnect lines. Scattering bars are not printed in the photoresist pattern. The process affords higher DOF, lower OPE, and less sensitivity to lens aberrations than conventional lithography methods. A data processing flow is provided which leads to a modified GDS layout for each of the two masks. A system for producing phase shifting layout data is also included.

Full sized scattering bar alt-PSM technique for IC manufacturing in sub-resolution era

Fabricating a dual-trench alternating phase shift mask (PSM) is disclosed. A chromium layer over a mask layer, which is over a quartz layer, of the PSM is patterned according to a semiconductor design. The mask layer is dry etched according to deep trenches of a PSM design. The quartz layer is dry etched a first number of times through a first photoresist layer applied over the chromium layer and patterned according to the deep trenches of the PSM design by using backside ultraviolet exposure. The mask layer is dry etched again, according to shallow trenches of the PSM design. The quartz layer is dry etched a second number of times through a second photoresist layer applied over the chromium layer and patterned according to the shallow trenches of the PSM design by using backside ultraviolet exposure.

Dual trench alternating phase shift mask fabrication

A method of forming contact holes in either a positive radiation sensitive layer, such as positive photoresist, or a negative radiation sensitive layer, such as negative photoresist, using three exposures is described. The sum of the three exposure doses is equal to that required to expose the entire radiation sensitive layer. The allowable contact hole locations are at the intersection of a first array of parallel regularly spaced lines and a second array of parallel regularly spaced lines. The lines are exposed in two separate exposures. For the positive radiation sensitive layer the contact holes are partially exposed by these exposures. For the negative radiation sensitive layer the contact holes remain unexposed by these exposures. The third exposure uses a pattern mask to either fully expose the contact holes in the positive radiation sensitive layer or leave them unexposed in the negative radiation sensitive layer. The radiation sensitive layer is then developed and the contact holes are formed.

Exposure method for the contact hole

Full sized scattering bar alt-PSM technique for IC manufacturing in sub-resolution ERA

A method for transferring a pattern from a mask to a substrate (or wafer), comprises dividing a mask generation data file into a plurality of segments. The segments include a main pattern area and a stitching area. Each stitching area contains a respective common pattern. An image of an illuminated portion of the main pattern area is formed. Connection ends of the segments in a substrate area (or wafer area) are illuminated with an illumination beam. An image of the illuminated portion of the main pattern area is formed, and a halftone gray level dosage distribution is produced in the substrate area (or wafer area) corresponding to the common pattern. The common patterns of adjacent segments substantially overlap in the substrate area (or wafer area).

Pattern compensation for stitching

Utilizing contact printing as the second exposure within a double exposure attenuated phase shift mask (APSM) fabrication process is disclosed. The process defines the shift pattern within the attenuated layer of the APSM using a first exposure, such as electron beam (e-beam) writing. The attenuated layer may be MoSi, MoSiO, and so on. The process then defines the border pattern within the opaque layer of the APSM using a second exposure. The second exposure employs contact printing, utilizing a contact exposure mask. The contact printing process may align the contact exposure mask over the wafer on which the APSM is fabricated utilizing a camera and an image storage system storing an image of this wafer.

Contact printing as second exposure of double exposure attenuated phase shift mask process

Employing a tri-tone attenuated phase shift trim mask in the second exposure of a double exposure alternating phase shift mask (alt-PSM) process is disclosed. A semiconductor wafer is first exposed utilizing a dark field alt-PSM, and then secondly is exposed utilizing a tri-tone attenuated PSM. The tri-tone attenuated PSM may include a transparent substrate, such as quartz, an opaque layer, such as chrome, and an attenuated layer, such as 6% transparency molybdenum silicide (MoSi). The opaque layer has a pattern corresponding to polysilicon gates to be imprinted on the semiconductor wafer, to protect the polysilicon photoresist patterns. The attenuated layer includes assist features to protect forbidden pitch semi-isolated field polysilicon patterns and isolated field polysilicon patterns to be imprinted on the semiconductor wafer.

Tri-tone attenuated phase shift trim mask for double exposure alternating phase shift mask process

A method of forming photomasks is described which provides good critical dimension control for critical pattern elements and provides good throughput and low defect levels for etching relatively large areas of opaque material. The pattern is first modified to form a frame around the pattern elements which require good critical dimension control. The opaque material, such as chrome, in this frame is then etched away using dry anisotropic etching. The dry anisotropic etching provides good critical dimension control. The remainder of the opaque material to be removed is then etched away using wet isotropic etching. The wet isotropic etching provides good defect control in this region of the mask and good throughput. This method provides good critical dimension control at the edges of the pattern elements, good throughput in mask fabrication, and good defect level control in removing the relatively large areas of opaque material which do not affect critical dimension control.

Chrome mask dry etching process to reduce loading effect and defects

The invention relates to fabricating a single-trench alternating phase shift mask (PSM). A chromium layer over a mask layer, which is itself over a quartz layer, of the PSM is patterned according to a semiconductor design. The mask layer and the quartz layer are dry etched through a photoresist layer that has been applied over the chromium layer and patterned according to an alternating PSM design. The dry etching initially forms single trenches of the PSM. The quartz layer is next wet etched through the mask layer to completely form the single trenches of the PSM, where the photoresist layer has first been removed. The mask layer is dry etched again, where the single trenches of the PSM are initially filled with filler material to protect the single trenches from the dry etching.

Single trench alternating phase shift mask fabrication

A process is described for shrinking gate lengths and poly interconnects simultaneously during the fabrication of an integrated circuit. A positive tone photoresist is coated on a substrate and is first exposed with an alternating phase shift mask that has full size scattering bars which enable a gate dimension to be printed that is &frac14; to &frac12; the size of the exposing wavelength. The substrate is then exposed using a tritone attenuated phase shift mask with a chrome blocking area to protect the shrunken gates and attenuated areas with scattering bars for shrinking the interconnect lines. Scattering bars are not printed in the photoresist pattern. The process affords higher DOF, lower OPE, and less sensitivity to lens aberrations than conventional lithography methods. A data processing flow is provided which leads to a modified GDS layout for each of the two masks. A system for producing phase shifting layout data is also included.

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Hsin-Chu, Taiwan

Chung-Hsing Chang