Taiwan Semiconductor Manufacturing Comp. Ltd.

Chung-Hao Tsai

Chuei-Tang Wang

Chen-Hua Douglas Yu

Jeng-Shien Hsieh

Tzu-Chun Tang

Kai-Chiang Wu

Wei-Ting Chen

Chih-Chieh Chang

Che-Wei Hsu

Shih-Ya Huang

En-Hsiang Yeh

Monsen Liu

Chun-Lin Lu

Chih-Yuan Chang

Ching-Hua Hsieh

Han-Ping Pu

Chieh-Yen Chen

Lai Wei Chih

Wei-Heng Lin

Chao-Wen Shih

Hsing-Kuo Hsia

Yen-Ping Wang

Albert Wan

Kuo-Chung Yee

Pei-Hsuan Lee

Chien-Ling Hwang

Yu-Ting Chiu

Jui-Chang Kuo

Chia-Chia Lin

Chun-Wen Lin

Jeng-Shieh Hsieh

Chung-Shi Liu

Yih Wang

Hsiu-Jen Lin

Shou-Zen Chang

Ming-Kai Liu

Chien-Hsun Chen

Chia-Lun Chang

Chih-Lin Chen

Hsin-Yu Pan

Lipu Kris Chuang

Yi-Che Chiang

Wei-Chih Lai

Chien-Chang Lin

Yeh En-Hsiang

A package assembly and a manufacturing method thereof are provided. The package assembly includes a first package component and an optical signal port disposed aside the first package component. The first package component includes a first die including an electronic integrated circuit, a first insulating encapsulation laterally covering the first die, a redistribution structure disposed on the first die and the first insulating encapsulation, and a second die including a photonic integrated circuit and electrically coupled to the first die through the redistribution structure. The optical signal port is optically coupled to an edge facet of the second die of the first package component.

Package assembly and manufacturing method thereof

A package structure includes at least one integrated circuit component, an insulating encapsulation, and a redistribution structure. The at least one integrated circuit component includes a semiconductor substrate, an interconnection structure disposed on the semiconductor substrate, and signal terminals and power terminals located on and electrically connecting to the interconnection structure. The interconnection structure is located between the semiconductor substrate and the signal terminals and between the semiconductor substrate and the power terminals, and where a size of the signal terminals is less than a size of the power terminals. The insulating encapsulation encapsulates the at least one integrated circuit component. The redistribution structure is located on the insulating encapsulation and electrically connected to the at least one integrated circuit component.

Package structure

A method includes forming a reconstructed wafer, which includes forming a redistribution structure over a carrier, bonding a first plurality of memory dies over the redistribution structure, bonding a plurality of bridge dies over the redistribution structure, and bonding a plurality of logic dies over the first plurality of memory dies and the plurality of bridge dies. Each of the plurality of bridge dies interconnects, and is overlapped by corner regions of, four of the plurality of logic dies. A second plurality of memory dies are bonded over the plurality of logic dies. The plurality of logic dies form a first array, and the second plurality of memory dies form a second array.

Architecture for computing system package

A semiconductor package includes electric integrated circuit dies, photoelectric integrated circuit dies, and an inter-chip waveguide. The electric integrated circuit dies are laterally encapsulated by a first insulating encapsulant. The photoelectric integrated circuit dies are laterally encapsulated by a second insulating encapsulant. Each one of photoelectric integrated circuit dies includes an optical input/output terminal. The inter-chip waveguide is disposed over the second insulating encapsulant, wherein the photoelectric integrated circuit dies are optically communicated with each other through the inter-chip waveguide.

Semiconductor package and method of forming the same

A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a photonic die, an encapsulant and a wave guide structure. The photonic die includes: a substrate, having a wave guide pattern formed at front surface; and a dielectric layer, covering the front surface of the substrate, and having an opening overlapped with an end portion of the wave guide pattern. The encapsulant laterally encapsulates the photonic die. The wave guide structure lies on the encapsulant and the photonic die, and extends into the opening of the dielectric layer, to be optically coupled to the wave guide pattern.

Semiconductor package and manufacturing method thereof

An electronic apparatus is provided. The electronic apparatus includes an integrated fan-out package, a dielectric housing, and a plurality of conductive patterns. The dielectric housing is covering the integrated fan-out package, wherein a gap or a first dielectric layer is in between the dielectric housing and the integrated fan-out package. The plurality of conductive patterns is located on a surface of the dielectric housing, wherein the plurality of conductive patterns is located in between the dielectric housing and the integrated fan-out package.

Electronic apparatus including antennas and directors

Semiconductor device includes light-emitting die and semiconductor package. Light emitting die includes substrate and first conductive pad. Substrate has emission region located at side surface. First conductive pad is located at bottom surface of substrate. Semiconductor package includes semiconductor-on-insulator substrate, interconnection structure, second conductive pad, and through semiconductor via. Semiconductor-on-insulator substrate has linear waveguide formed therein. Interconnection structure is disposed on semiconductor-on-insulator substrate. Edge coupler is embedded within interconnection structure and is connected to linear waveguide. Semiconductor-on-insulator substrate and interconnection structure include recess in which light-emitting die is disposed. Edge coupler is located close to sidewall of recess. Second conductive pad is located at bottom of recess. Through semiconductor via extends across semiconductor-on-insulator substrate to contact second conductive pad. First conductive pad is connected to through semiconductor via. Emission region directly faces sidewall of recess where edge coupler is located.

Semiconductor device and manufacturing method thereof

A package structure includes a semiconductor die, an antenna substrate structure, a redistribution layer. The semiconductor die laterally encapsulated by a first encapsulant. The antenna substrate structure disposed over the semiconductor die, wherein the antenna substrate structure includes a first type of antenna, and a second type of antenna disposed on a side of the antenna substrate structure facing away from the semiconductor die. The redistribution layer disposed between the semiconductor die and the antenna substrate structure. The semiconductor die, the first type of antenna, and the second type of antenna are electrically coupled through the redistribution layer. The polarization of radiation emitted by the first type of antenna is perpendicular to a polarization of radiation emitted by the second type of antenna.

Package structure and manufacturing method thereof

In an embodiment, a method includes: bonding a back side of a first memory device to a front side of a second memory device with dielectric-to-dielectric bonds and with metal-to-metal bonds; after the bonding, forming first conductive bumps through a first dielectric layer at a front side of the first memory device, the first conductive bumps raised from a major surface of the first dielectric layer; testing the first memory device and the second memory device using the first conductive bumps; and after the testing, attaching a logic device to the first conductive bumps with reflowable connectors.

Integrated circuit packages

A method includes thinning a semiconductor substrate of a device die to reveal through-substrate vias that extend into the semiconductor substrate, and forming a first redistribution structure, which includes forming a first plurality of dielectric layers over the semiconductor substrate, and forming a first plurality of redistribution lines in the first plurality of dielectric layers. The first plurality of redistribution lines are electrically connected to the through-substrate vias. The method further includes placing a first memory die over the first redistribution structure, and forming a first plurality of metal posts over the first redistribution structure. The first plurality of metal posts are electrically connected to the first plurality of redistribution lines. The first memory die is encapsulated in a first encapsulant. A second plurality of redistribution lines are formed over, and electrically connected to, the first plurality of metal posts and the first memory die.

Die stacks and methods forming same

A method includes bonding a capacitor die to a device die. The device die includes a first semiconductor substrate, active devices at a surface of the first semiconductor substrate, a plurality of low-k dielectric layers, a first dielectric layer over and contacting a top low-k dielectric layer in the plurality of low-k dielectric layers, and a first plurality of bond pads in the first dielectric layer. The capacitor die includes a second dielectric layer bonding to the first dielectric layer, a second plurality of bond pads in the second dielectric layer and bonding to the first plurality of bond pads, and a capacitor electrically coupled to the second plurality of bond pads. After the capacitor die is bonded to the device die, an aluminum-containing pad is formed over the capacitor die and electrically coupled to the device die. A polymer layer is formed over the aluminum-containing pad.

Deep partition power delivery with deep trench capacitor

An antenna device includes a radio frequency (RF) die, a first dielectric layer, a feeding line, a ground line, a second dielectric layer, and a radiating element. The first dielectric layer is over the RF die. The feeding line is in the first dielectric layer and is connected to the RF die. The ground line is in the first dielectric layer and is spaced apart from the feeding line. The second dielectric layer covers the first dielectric layer. The radiating element is over the second dielectric layer and is not in physically contact with the feeding line.

Antenna device

A package structure and a manufacturing method thereof are provided. The package structure includes a carrier substrate, an integrated circuit (IC) die thermally coupled to the carrier substrate through a thermally conductive layer, an antenna pattern disposed over the carrier substrate and the IC die, a redistribution structure disposed between the antenna pattern and the IC die, and an underfill disposed below and thermally coupled to the carrier substrate. The antenna pattern is electrically coupled to the IC die.

Package structure comprising thermally conductive layer around the IC die

An embodiment is a device including an integrated circuit die having an active side and a back side, the back side being opposite the active side, a molding compound encapsulating the integrated circuit die, and a first redistribution structure overlying the integrated circuit die and the molding compound, the first redistribution structure including a first metallization pattern and a first dielectric layer, the first metallization pattern being electrically coupled to the active side of the integrated circuit die, at least a portion of the first metallization pattern forming an inductor.

Semiconductor packages having a die, an encapsulant, and a redistribution structure

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Changhua County, Taiwan

Chung-Hao Tsai