Taiwan Semiconductor Manufacturing Comp. Ltd.

Fitipower Integrated Technology, Inc.

Chung-Hao Chang

Li-Kong Turn

Fei-Gwo Tsai

Jui-Ping Chuang

Ming-Shane Lu

Yi-Rem Chen

Ming-Wei Chen

Ching-Yueh Chen

Chih-Jen Yu

Keh-Wen Chang

Chung-Hsiao Hsieh

Li-Shiuan Chen

Chitong Chen

Han-Ming Hsieh

Ai-Jay Ma

In a method of manufacturing a semiconductor device, in an EUV scanner, an EUV lithography operation using an EUV mask is performed on a photo resist layer formed over a semiconductor substrate. After the EUV lithography operation, the EUV mask is unloaded from a mask stage of the EUV scanner. The EUV mask is placed under a reduced pressure below an atmospheric pressure. The EUV mask is heated under the reduced pressure at a first temperature in a range from 100° C. to 350 C°. After the heating, the EUV mask is stored in a mask stocker.

Method of manufacturing semiconductor devices using a photomask

A developing method is provided. The developing method includes rotating a wafer. The developing method also includes dispensing, through a first nozzle, a developer solution onto the rotated wafer through a first nozzle at a first rotating speed. The developing method further includes dispensing, through a second nozzle, a rinse solution onto the rotated wafer through a second nozzle at a second rotating speed. The second rotating speed is less than the first rotating speed. In addition, the developing method includes simultaneously moving the first nozzle and the second nozzle during either the dispensing of the developer solution or the dispensing of the rinse solution.

Developing method

A method of treating a semiconductor substrate includes converting a first main side of the semiconductor substrate having a first coefficient of static friction relative to a surface of a wafer table to a second coefficient of static friction relative to the surface of the wafer table, wherein the second coefficient of static friction is less than the first coefficient of static friction. A photoresist layer is applied over a second main side of the semiconductor substrate having the first coefficient of static friction. The second main side opposes the first main side. The semiconductor substrate is placed on the wafer table so that the first main side of the semiconductor substrate faces the wafer table.

Method of treating semiconductor substrate

A method of manufacturing a semiconductor device is disclosed. In the method, a metallic layer is formed over a substrate, the metallic layer is surface-treated with an alkaline solution, and a bottom anti-reflective coating (BARC) layer is formed on the surface-treated metallic layer.

Treatment to interface between metal film and BARC or photoresist

A developing method comprises steps as follows. A wafer is rotated. A developer solution is dispensed onto the rotated wafer through a first nozzle. The first nozzle is moved back and forth between a first position and a second position, in which moving the first nozzle back and forth is performed such that the first nozzle moving forward to the second position is reversed at the second position and that the first nozzle moving forward to the first position is reversed at the first position, and the first position and the second position are directly over the wafer, and the developer solution is dispensed through the first nozzle when moving the first nozzle back and forth between the first position and the second position.

A developing method includes rotating a wafer. A developer solution is dispensed onto the rotated wafer through a first nozzle. The first nozzle is moved from a first position to a second position. The first position and the second position are over the wafer and within a perimeter of the wafer when viewed from a top of the wafer. The developer solution is dispensed through the first nozzle when moving the first nozzle from the first position to the second position. The first nozzle is moved back from the second position to the first position immediately after the first nozzle is moved from the first position to the second position. The developer solution is dispensed through the first nozzle when moving the first nozzle from the second position to the first position.

A tool and a method of developing are provided. In various embodiments, the method of developing includes rotating a wafer at a first rotating speed. The method further includes dispensing a developer solution onto the wafer at the first rotating speed by a first nozzle above the wafer, wherein the first nozzle moves back and forth along a path during dispensing the developer solution. The method further includes rotating the wafer at a second rotating speed to spread the developer solution onto the wafer uniformly. The method further includes dispensing a rinse solution onto the wafer at the second rotating speed by a second nozzle above the wafer.

Tool and method of developing

A display apparatus includes a receiving module, a processing module, a selecting module, a power circuit, and a backlight module. The receiving module receives a pulse width modulating (PWM) signal from an external component. The processing module processes the PWM signal in a predetermined time duration. The selecting module outputs the unadjusted PWM signal to the power circuit in the predetermined time duration, and outputs an adjusted signal after the predetermined duration. The power circuit generates a first driving current for driving the backlight module to emit lights in response to the unadjusted PWM signal while the processing module processes the PWM signal. The backlight module remains a predetermined brightness after the predetermined time.

Display apparatus and backlight driving module

One embodiment relates to a method to achieve enhanced overlay control while maintaining manufacturing throughput for a fabrication process. Locations of a plurality of alignment structures on a wafer comprising a plurality of reticle fields are determined with a layout tool to define a layout-based wafer map. The topography of the wafer is then measured as a function of wafer position by a surface measuring tool. The layout-based wafer map is then projected onto the measured wafer topography to define a modeled wafer map. A subset of alignment structure locations are measured with an alignment tool in an in-line fabrication flow so as not to delay subsequent fabrication steps. Disagreement between the measured alignment structure locations and modeled alignment structure locations is then minimized mathematically to enhance overlay control while maintaining manufacturing throughput.

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Hsinchu, Taiwan

Chung-Hao Chang