Globalfoundries Inc.

Globalfoundries U.S. Inc.

Chung Foong Tan

Ruilong Xie

Hui Zang

Haiting Wang

Scott Beasor

Guowei Xu

Maciej Wiatr

Tek Po Rinus Lee

Yue Zhong

Shesh Mani Pandey

Peter Javorka

George Robert Mulfinger

Ryan W Sporer

Baofu Zhu

Nicolas Sassiat

Arkadiusz Malinowski

Liu Jiang

Falong Zhou

A structure and method use different stress-inducing isolation dielectrics to induce appropriate stresses in different polarity FETs to improve performance of both type FETs. The structure may include a first stress-inducing isolation dielectric surrounding and contacting a first active region for a p-type field effect transistor (PFET), and a second stress-inducing isolation dielectric surrounding and contacting a second active region for an n-type field effect transistor (NFET). The first and second stress-inducing isolation dielectrics induce different types of stress, thus improving performance of both polarity of FETs.

Structure with different stress-inducing isolation dielectrics for different polarity FETs

The present disclosure relates to semiconductor structures and, more particularly, to n-well resistors and methods of manufacture. The structure includes: a substrate composed of a N-well implant region and a deep N-well implant region; and a plurality of shallow trench isolation regions extending into both the N-well implant region and a deep N-well implant region.

N-well resistor

An integrated circuit product is disclosed that includes a transistor device that includes a final gate structure, a gate cap, a low-k sidewall spacer positioned on and in contact with opposing sidewalls of the final gate structure, first and second contact etch stop layers (CESLs) located on opposite sides of the final gate structure, whereby the CESLs are positioned on and in contact with the low-k sidewall spacer, and a high-k spacer located on opposite sides of the final gate structure, wherein the high-k spacer is positioned in recesses formed in an upper portion of the CESLs.

Spacer structures for a transistor device

A FinFET structure having reduced effective capacitance and including a substrate having at least two fins thereon laterally spaced from one another, a metal gate over fin tops of the fins and between sidewalls of upper portions of the fins, source/drain regions in each fin on opposing sides of the metal gate, and a dielectric bar within the metal gate located between the sidewalls of the upper portions of the fins, the dielectric bar being laterally spaced away from the sidewalls of the upper portions of the fins within the metal gate.

FinFET structure with dielectric bar containing gate to reduce effective capacitance, and method of forming same

One illustrative method disclosed herein includes forming a low-k sidewall spacer adjacent opposing sidewalls of a gate structure, forming contact etch stop layers (CESLs) adjacent the low-k sidewall spacer in the source/drain regions of the transistor, and forming a first insulating material above the CESLs. In this example, the method also includes recessing the first insulating material so as to expose substantially vertically oriented portions of the CESLs, removing a portion of a lateral width of the substantially vertically oriented portions of the CESLs so as to form trimmed CESLs, and forming a high-k spacer on opposite sides of the gate structure, wherein at least a portion of the high-k spacer is positioned laterally adjacent the trimmed substantially vertically oriented portions of the trimmed CESLs.

Methods of forming spacers adjacent gate structures of a transistor device

A method includes providing a semiconductor structure including a substrate, a gate structure over the substrate and a sidewall spacer adjacent the gate structure. The substrate includes a first semiconductor material. A substantially isotropic first etch process removing the first semiconductor material is performed. The first etch process forms an undercut below the sidewall spacer. An anisotropic second etch process removing the first semiconductor material is performed, wherein an etch rate in a thickness direction of the substrate is greater than an etch rate in a horizontal direction that is perpendicular to the thickness direction. A crystallographic third etch process removing the first semiconductor material is performed, wherein an etch rate in a first crystal direction is greater than an etch rate in a second crystal direction. The first, second and third etch processes form a source-side recess and a drain-side recess adjacent the gate structure.

Semiconductor structure including a transistor having stress creating regions and method for the formation thereof

Methods of forming transistor devices having an increased gate width dimension are disclosed. In one example, the method includes forming an isolation structure in a semiconducting substrate, wherein the isolation structure defines an active region in the substrate, performing an ion implantation process on the isolation structure to create a damaged region in the isolation structure and, after performing the implantation process, performing an etching process to remove at least a portion of the damaged region to define a recess in the isolation structure, wherein a portion of the recess extends below an upper surface of the substrate and exposes a sidewall of the active region. The method further includes forming a gate insulation layer above the active region, wherein a portion of the insulation layer extends into the recess, and forming a gate electrode above the insulation layer, wherein a portion of the gate electrode extends into the recess.

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Ballston Spa, NY, United States of America

Chung Foong Tan