Yangtze Memory Technologies Co., Ltd.

Chun Yuan Hou

Yue Ping Li

Qiang Tang

Ke Liang

Yueping Li

Wei Jun Wan

A three-dimensional (3D) memory device includes a 3D NAND memory array, an on-die static random-access memory (SRAM), and peripheral circuits formed on the same chip with the on-die SRAM. The peripheral circuits include a page buffer coupled to the on-die SRAM and a controller coupled to the on-die SRAM and the page buffer. The controller may be configured to load program data into the page buffer and cache the program data into the on-die SRAM as a backup copy of the program data. In response to a status of programming the program data from the page buffer into the 3D NAND memory array being failed, the controller may be further configured to transmit the backup copy of the program data in the on-die SRAM to the page buffer, and program the backup copy of the program data in the page buffer into the 3D NAND memory array.

Cache program operation of three-dimensional memory device with static random-access memory

Embodiments of a three-dimensional (3D) memory device and a method of operating the 3D memory device are provided. The 3D memory device includes an array of 3D NAND memory cells, an array of static random-access memory (SRAM) cells, and a peripheral circuit. The array of SRAM cells and the peripheral circuit arranged at one side are bonded with the array of 3D NAND memory cells at another side to form a chip. Data is received from a host through the peripheral circuit, buffered in the array of SRAM cells, and transmitted from the array of SRAM cells to the array of 3D NAND memory cells. The data is programmed into the array of 3D NAND memory cells.

Data buffering operation of three-dimensional memory device with static random-access memory

Embodiments of 3D memory devices with a static random-access memory (SRAM) and fabrication methods thereof are disclosed herein. In certain embodiments, the 3D memory device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes an array of SRAM cells and a first bonding layer, and the second semiconductor structure includes an array of 3D NAND memory strings and a second bonding layer. The first semiconductor structure is attached with the second semiconductor structure through the first bonding layer and the second bonding layer. The array of 3D NAND memory strings and the array of SRAM cells are coupled through a plurality of bonding contacts in the first bonding layer and the second bonding layer and are arranged at opposite sides of the plurality of bonding contacts.

Three-dimensional memory device with static random-access memory

Embodiments of three-dimensional (3D) memory devices with a 3D NAND memory array having a plurality of pages, an on-die cache coupled to the memory array on a same chip and configured to cache a plurality of batches of program data between a host and the memory array, the on-die cache having SRAM cells, and a controller coupled to the on-die cache on the same chip. The controller is configured to check a status of an (N&#x2212;2)batch of program data, N being an integer equal to or greater than 2, program an (N&#x2212;1)batch of program data into respective pages in the 3D NAND memory array, and cache an Nbatch of program data in respective space in the on-die cache as a backup copy of the Nbatch of program data.

Embodiments of three-dimensional (3D) memory devices with a 3D NAND memory array having a plurality of pages and an on-die data buffer coupled to the memory array on a same chip and configured to buffer a plurality of batches of program data between a host and the memory array. The on-die data buffer may include SRAM cells. The 3D memory device also includes a controller coupled to the on-die data buffer on the same chip. The controller may be configured to receive control instructions for performing a first pass program and a second pass program on memory cells in a page. The controller may also be configured to buffer, in the on-die data buffer, first program data for a first pass program and second program data for a second pass program from a host and retrieve the first program data from the on-die data buffer.

Embodiments of 3D memory devices with a static random-access memory (SRAM) and fabrication methods thereof are disclosed herein. In one example, the method for operating a 3D memory device having an input/output circuit, an array of SRAM cells, and an array of 3D NAND memory strings in a same chip. The method may include transferring data through the input/output circuit to the array of SRAM cells, storing the data in the array of SRAM cells, and programming the data into the array of 3D NAND memory strings from the array of SRAM cells.

A method for programming a memory system including a plurality of memory cells includes performing a first program operation on the plurality of the memory cells. The method also includes identifying a first memory cell and a second set of memory cell from the plurality of memory cells based on threshold voltages of the plurality of memory cells after performing the first program operations. The method further includes performing a second operation on the plurality of the memory cells by applying a first cross voltage to the first memory cell and a second cross voltage to the second memory cell.

Method for programming memory system

A memory system comprising a plurality of memory cells each including a storage element having a first terminal and a control terminal. The method for operating the memory system includes applying a first program voltage to control terminals of storage elements and applying a basic reference voltage to first terminals of the storage elements during a first program operation, performing a group verification by comparing threshold voltages of the storage elements with a middle voltage, performing a first program test to check if the threshold voltages of the storage elements are greater than a first programming threshold voltage, and performing a second program operation according to a result of the group verification and a result of the first program test. The middle voltage is smaller than the first programming threshold voltage.

Embodiments of three-dimensional (3D) memory devices with a 3D memory device includes a first semiconductor structure having a peripheral circuit, an array of SRAM cells, and a first bonding layer having a plurality of first bonding contacts. The 3D memory device also includes a second semiconductor structure having an array of 3D NAND memory strings and a second bonding layer including a plurality of second bonding contacts and a bonding interface between the first bonding layer and the second bonding layer, wherein the first bonding contacts are in contact with the second bonding contacts at the bonding interface.

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Wuhan, China

Chun Yuan Hou