United Microelectronics Corp.

United Silicon Incorporated

Fujian Jinhua Integrated Circuit Co., Ltd.

Chun-Liang Liu

Po-Cheng Huang

Hsien-Liang Meng

Fu-Shou Tsai

Shih-Ming Lan

Kun-Ju Li

Yu-Ting Li

Wen-Chin Lin

Li-Chieh Hsu

Andrew Lin

A planarization method is provided and includes the following steps. A substrate having a main surface is provided. A protruding structure is formed on the main surface. An insulating layer is formed conformally covering the main surface and the top surface and the sidewall of the protruding structure. A stop layer is formed on the insulating layer and at least covers the top surface of the protruding structure. A first dielectric layer is formed blanketly covering the substrate and the protruding structure and a chemical mechanical polishing process is then performed to remove a portion of the first dielectric layer until a portion of the stop layer is exposed thereby obtaining an upper surface. A second dielectric layer having a pre-determined thickness is formed covering the upper surface.

Planarization method

The present invention provides a wafer polishing pad, the wafer polishing pad includes a polishing material layer, a plurality of recesses are formed on the top surface of the polishing material layer, and a warning element disposed within the polishing material layer, the warning element and the polishing material layer have different colors. The feature of the invention is that forming a warning element in the polishing material layer, when the visible state of the warning element is changed, for example, when the warning element appears, disappears or changes the shapes, it means that the wafer polishing pad needs to be replaced. In this way, the user can confirm the destroying situation of the wafer polishing pad easily, and also improving the manufacturing process efficiency.

Wafer polishing pad and using method thereof

A method for manufacturing metal interconnects. The method includes following steps. A substrate including a dielectric layer formed thereon is provided, and a plurality of trenches are formed in the dielectric layer. Next, a seed layer is formed in the trenches and on the dielectric layer and followed by masking regions of the seed layer to define a plurality of masked regions and a plurality of exposed regions for the seed layer. Subsequently, a surface treatment is performed to the exposed regions of the seed layer to form a plurality of rough surfaces on the exposed regions of the seed layer. Then, a metal layer is formed on the substrate, and the trenches are filled up with the metal layer.

Method for manufacturing metal interconnects

A method of fabricating a shallow trench isolation structure is described. A mask layer is formed on a substrate. The mask layer and the substrate are patterned to form a trench in the substrate. A first deposition step and a second deposition step are performed to form a first isolation layer over the substrate. A third deposition step is performed to form a second isolation layer on the first isolation layer. The second isolation layer has a greater fluidity than the first isolation layer has. A planarization process is performed with the mask layer serving as a stop layer. A portion of the first isolation layer and the mask layer are removed to form the shallow trench isolation structure.

Method of fabricating shallow trench isolation structure

A method for manufacturing a shallow trench isolation. A substrate is provided, wherein the substrate has a pad oxide on the substrate and a silicon nitride layer on the pad oxide layer, and a trench penetrates through the silicon oxide layer and the pad oxide layer and into the substrate. A first oxide layer is conformally formed on the silicon nitride layer and in the trench. A rapid thermal process is performed. A second oxide layer is formed on the oxide layer to fill the trench. Portions of the first and the second oxide layers are removed to expose the silicon nitride layer.

Method of manufacturing shallow trench isolation

A method for forming an insulating layer to solve a problem of non-uniform thickness of the insulating layer is provided. The method includes forming a first insulating layer over a substrate preferably by chemical vapor deposition (CVD) at an operation temperature of about 200&deg; C.-350&deg; C. The thickness of the first insulating layer is about 500 &angst;-5000 &angst;. A second insulating layer is formed over the first insulating layer preferably by CVD at a temperature of about 350&deg; C.-500&deg; C. The thickness of the second insulating layer is about 1000 &angst;-10000 &angst;. The first and the second insulating layers form together as an insulating layer to insulate transistors and isolation structures from the interconnect metal layer.

Growing community of inventors

Hsinchu, Taiwan

Chun-Liang Liu