Taiwan Semiconductor Manufacturing Comp. Ltd.

Chun-Kai Chen

Tze-Liang Lee

Jung-Hau Shiu

Chung-Chi Ko

Chih-Hao Chen

Shing-Chyang Pan

Szu-Ping Tung

Chia Cheng Chou

Yi-Nien Su

Jei Ming Chen

Ching-Yu Chang

Jen Hung Wang

JeiMing Chen

A method includes depositing a first dielectric layer over a first conductive feature, depositing a first mask layer over the first dielectric layer, and depositing a second mask layer over the first mask layer. A first opening is patterned in the first mask layer and the second mask layer, the first opening having a first width. A second opening is patterned in a bottom surface of the first opening, the second opening extending into the first dielectric layer, the second opening having a second width. The second width is less than the first width. The first opening is extended into the first dielectric layer and the second opening is extended through the first dielectric layer to expose a top surface of the first conductive feature.

Method for forming interconnect structure

In one exemplary aspect, the present disclosure is directed to a method for lithography patterning. The method includes providing a substrate and forming a target layer over the substrate. A patterning layer is formed by depositing a first layer having an organic composition; depositing a second layer including over 50 atomic percent of silicon; and depositing a photosensitive layer on the second layer. In some implementations, the second layer is deposited by ALD, CVD, or PVD processes.

Patterning material including silicon-containing layer and method for semiconductor device fabrication

A method includes forming a metal-containing hard mask layer over a dielectric layer, wherein the metal-containing hard mask layer has a Young's modulus greater than about 400 MPa and a tensile stress greater than about 600 MPa, patterning the metal-containing hard mask layer to form an opening in the metal-containing hard mask layer, and etching the dielectric layer using the metal-containing hard mask layer as an etching mask. The opening extends into the dielectric layer. The opening is filled with a conductive material to form a conductive feature. The metal-containing hard mask layer is then removed.

Metal hard masks for reducing line bending

A method includes forming a carbon-containing layer with a carbon atomic percentage greater than about 25 percent over a first hard mask layer, forming a capping layer over the carbon-containing layer, forming a first photo resist over the capping layer, and etching the capping layer and the carbon-containing layer using the first photo resist as a first etching mask. The first photo resist is then removed. A second photo resist is formed over the capping layer. The capping layer and the carbon-containing layer are etched using the second photo resist as a second etching mask. The second photo resist is removed. A third photo resist under the carbon-containing layer is etched using the carbon-containing layer as etching mask. A dielectric layer underlying the third photo resist is etched to form via openings using the third photo resist as etching mask. The via openings are filled with a conductive material.

Multi-patterning to form vias with straight profiles

A hard mask formed over a patterned photoresist layer in a tri-layer photoresist and a method for patterning a target layer using the same are disclosed. In an embodiment, a method includes depositing a photoresist layer over a first hard mask layer; patterning the photoresist layer to form a plurality of openings in the photoresist layer; depositing a second hard mask layer over the photoresist layer, the second hard mask layer filling the plurality of openings, the second hard mask layer having a first etch selectivity relative to the first hard mask layer, the photoresist layer having a second etch selectivity relative to the first hard mask layer, the first etch selectivity being greater than the second etch selectivity; planarizing the second hard mask layer; removing the photoresist layer; and etching the first hard mask layer using the second hard mask layer as a mask.

Patterning method for semiconductor devices and structures resulting therefrom

A method includes forming a carbon-containing layer with a carbon atomic percentage greater than about 25 percent over a first hard mask layer, forming a capping layer over the carbon-containing layer, forming a first photo resist over the capping layer, and etching the capping layer and the carbon-containing layer using the first photo resist as a first etching mask. The first photo resist is then removed. A second photo resist is formed over the capping layer. The capping layer and the carbon-containing layer are etched using the second photo resist as a a second etching mask. The second photo resist is removed. A third photo resist under the carbon-containing layer is etched using the carbon-containing layer as etching mask. A dielectric layer underlying the third photo resist is etched to form via openings using the third photo resist as etching mask. The via openings are filled with a conductive material.

Growing community of inventors

Kaohsiung, Taiwan

Chun-Kai Chen