Taiwan Semiconductor Manufacturing Comp. Ltd.

Macronix International Co., Ltd.

Chun-Jung Lin

Ya-Chen Kao

Yu-Jen Wang

Shine Chien Chung

Tao-Wen Chung

Hung-Chang Yu

Kai-Chun Lin

Chun-Yi Yang

Hung-Sen Wang

Ming-Te Liu

Yu-Der Chih

Yue-Der Chih

Tien-Wei Chiang

Wen-Cheng Chen

Fu-Lung Hsueh

Sheng-Huang Huang

Jun-De Jin

Tong-Chern Ong

Mam-Tsung Wang

Kuo-Feng Huang

Chih-Huang Lai

Sa-Lly Liu

Ful-Long Ni

Ping-Lin Yang

Jui-Chin Chang

Harry-Hak-Lay Chuang

Cheng-Yuan Tsai

Chih-Ming Chen

Chung-Yi Yu

William Joseph Gallagher

Samuel C Pan

Feng-Jia Shiu

Kuei-Hung Shen

Chin-Yi Huang

Tso-Hung Fan

Meng-Chun Shih

Yen-Hung Yeh

Ching-Huang Wang

Chia-Hsing Chen

Shui-Chin Huang

Yun-Sheng Chen

Hsu-Chen Cheng

Yung-Tao Lin

Lee-Wei Yen

Young-Shying Chen

Chang-Ju Chen

Minnie Hsiung

Bing-Ying Wang

Ping-Ying Wang

Chun-Hon Chen

Shi-Chung Sun

Chia-Yu Wang

The disclosure is related a method for testing a magnetic memory device and a test apparatus are provided. In some exemplary embodiments, the method includes at least the following steps. The magnetic memory device is initialized by applying a first magnetic field to force write a first data to the magnetic memory device. Then, a second magnetic field is applied to the magnetic memory device. Second data may be obtained from the magnetic memory device by performing a chip probing process. Accordingly, performance of the magnetic memory device may be determined based on the second data.

Method for testing MRAM device and test apparatus thereof

A method includes applying a first voltage to a first source line of a memory, applying a second voltage to a second source line of the memory, turning on an access transistor of a memory cell of the memory, and performing one of a write operation or a read operation on a metal-ferroelectric-semiconductor (MFS) transistor of the memory cell. Memories on which the method is performed are also disclosed.

Memories with metal-ferroelectric-semiconductor (MFS) transistors

A method for controlling a magnetic memory device is provided. The method includes: applying a first control signal and a second control signal to a ferromagnetic fixed layer and a ferromagnetic free layer of the magnetic memory device respectively, wherein a first voltage level of the first control signal is lower than a second voltage level of the second control signal; sensing a first current signal flowing through the magnetic memory device; and determining a logical state of a first data bit according to the first current signal.

Semiconductor memory device and method for controlling the same

A communications structure comprises a first semiconductor substrate having a first coil, and a second semiconductor substrate having a second coil above the first semiconductor substrate. Inner edges of the first and second coils define a boundary of a volume that extends below the first coil and above the second coil. A ferromagnetic core is positioned at least partially within the boundary, such that a mutual inductance is provided between the first and second coils for wireless transmission of signals or power between the first and second coils.

Contactless communications using ferromagnetic material

One method includes forming an anti-ferromagnetic layer on a substrate. A ferromagnetic layer may be formed on the anti-ferromagnetic layer. The ferromagnetic layer includes a first, second and third portions where the second portion is located between the first and third portions. A first ion irradiation is performed to only one portion of the ferromagnetic layer. A second ion irradiation is performed to another portion of the ferromagnetic layer.

Method of fabricating a magnetoresistive random access structure

A magnetoresistive memory has first and second magnetic tunnel junction (MTJ) elements operated differentially, each with a pinned magnetic layer and a free magnetic layer that can have field alignments that are parallel or anti-parallel, producing differential high and low resistance states representing a bit cell value. Writing a high resistance state to an element requires an opposite write current polarity through the pinned and free layers, and differential operation requires that the two MTJ elements be written to different resistance states. One aspect is to arrange or connect the layers in normal and reverse order relative to a current bias source, thereby achieving opposite write current polarities relative to the layers using the same current polarity relative to the current bias source. The differentially operated MTJ elements can supplement or replace single MTJ elements in a nonvolatile memory bit cell array.

Differential MRAM structure with relatively reversed magnetic tunnel junction elements enabling writing using same polarity current

Magneto-resistive memory bit cells in an array have high or low resistance states storing logic values. During read operations, a bias source is coupled to an addressed memory word, coupling a parameter related to cell resistance to a sense amplifier at each bit position. The sense amplifiers determine whether the parameter value is greater or less than a reference value between the high and low resistance states. The reference value is derived by averaging or splitting a difference of resistances of reference cells at high and/or low resistance states. Bias current is conducted over address lines with varying resistance, due to different distances between the sense amplifiers and addressed memory words, which is canceled by inserting into the comparison circuit a resistance from a dummy addressing array, equal to the resistance of the conductor addressing the selected word line and bit position.

Adjusting reference resistances in determining MRAM resistance states

A method of operating magneto-resistive random access memory (MRAM) cells includes providing an MRAM cell, which includes a magnetic tunneling junction (MTJ) device; and a selector comprising a source-drain path serially coupled to the MTJ device. The method further includes applying an overdrive voltage to a gate of the selector to turn on the selector.

Raising programming currents of magnetic tunnel junctions using word line overdrive and high-k metal gate

MTJ stack structures for an MRAM device include an MTJ stack having a pinned ferromagnetic layer over a pinning layer, a tunneling barrier layer over the pinned ferromagnetic layer, a free ferromagnetic layer over the tunneling barrier layer, a conductive oxide layer over the free ferromagnetic layer, and an oxygen-based cap layer over the conductive oxide layer.

Structure and method for a MRAM device with an oxygen absorbing cap layer

Test structures, methods of manufacturing thereof, test methods, and magnetic random access memory (MRAM) arrays are disclosed. In one embodiment, a test structure is disclosed. The test structure includes an MRAM cell having a magnetic tunnel junction (MTJ) and a transistor coupled to the MTJ. The test structure includes a test node coupled between the MTJ and the transistor, and a contact pad coupled to the test node.

Test structures, methods of manufacturing thereof, test methods, and MRAM arrays

A reference circuit discerns high or low resistance states of a magneto-resistive memory element such as a bit cell. The reference circuit has magnetic tunnel junction (MTJ) elements in complementary high and low resistance states Rand R, providing a voltage, current or other parameter for comparison against the memory element to discern a resistance state. The parameter represents an intermediate resistance straddled by Rand R, such as an average or twice-parallel resistance. The reference MTJ elements are biased from the same read current source as the memory element but their magnetic layers are in opposite order, physically or by order along bias current paths. The reference MTJ elements are biased to preclude any read disturb risk. The memory bit cell is coupled to the same bias polarity source along a comparable path, being safe from read disturb risk in one of its two possible logic states.

Reference cell configuration for sensing resistance states of MRAM bit cells

A semiconductor memory device includes a first ferromagnetic layer magnetically pinned and positioned within a first region of a substrate; a second ferromagnetic layer approximate the first ferromagnetic layer; and a barrier layer interposed between the first ferromagnetic layer and the first portion of the second ferromagnetic layer. The second ferromagnetic layer includes a first portion being magnetically free and positioned within the first region; a second portion magnetically pinned to a first direction and positioned within a second region of the substrate, the second region contacting the first region from a first side; and a third portion magnetically pinned to a second direction and positioned within a third region of the substrate, the third region contacting the first region from a second side.

Domain wall assisted spin torque transfer magnetresistive random access memory structure

A magnetic tunnel junction (MTJ) etching process uses a sacrifice layer. An MTJ cell structure includes an MTJ stack with a first magnetic layer, a second magnetic layer, and a tunnel barrier layer in between the first magnetic layer and the second magnetic layer, and a sacrifice layer adjacent to the second magnetic layer, where the sacrifice layer protects the second magnetic layer in the MTJ stack from oxidation during an ashing process. The sacrifice layer does not increase a resistance of the MTJ stack. The sacrifice layer can be made of Mg, Cr, V, Mn, Ti, Zr, Zn, or any alloy combination thereof, or any other suitable material. The sacrifice layer can be multi-layered and/or have a thickness ranging from 5 &#x212b; to 400 &#x212b;. The MTJ cell structure can have a top conducting layer over the sacrifice layer.

Sacrifice layer structure and method for magnetic tunnel junction (MTJ) etching process

A magnetoresistive memory stores logic values in high and low resistance states of magnetic tunnel junction elements. Instead of comparing the resistance of elements to a fixed threshold to discern a logic state, the resistances of elements are self-compared before and after imposing a low resistance state. A measure of the resistance of an element in its unknown resistance state is stored, for example by charging a capacitor to a voltage produced when read current bias is applied. Then the element is written into its low resistance state and read current bias is applied again to develop another voltage, representing the low resistance state. A comparison circuit using current summing and an offset providing a minimum difference tolerance determines whether the resistance of the element was changed or remained the same. This determines the logic state of the element.

MRAM with current-based self-referenced read operations

Growing community of inventors

Hsinchu, Taiwan

Chun-Jung Lin