Chipmos Technologies Inc.

Chipmos Technologies (bermuda) Ltd

National Cheng-kung University

Chun-Hung Lin

Geng-Shin Shen

Shih-Wen Chou

Yu-Tang Pan

An-Hong Liu

Yi-Chang Lee

Hsiang-Ming Huang

Wu-Chang Tu

Kuang-Hui Chen

Jesse Huang

Yeong-Jyh Lin

Wen-Yu Chen

Shih Feng Chiu

A method for a localized surface plasmon resonance (LSPR) sensing system is disclosed. The LSPR sensing system has an optical detection system and a test specimen with metal nanoparticles arranged in an anisotropic periodic manner that generates a phase signal of the LSPR sensing system. The method includes: emitting an incident light toward the test specimen to excite the metal nanoparticles, thereby generating an emergent light; using the optical detection system to detect phases of a first polarization state and a second polarization state of the emergent light, where the first polarization state is perpendicular to the second polarization state; and obtaining a phase difference spectrum between the phases of the first and second polarization states, thereby determining a half maximum (FWHM) of the phase difference spectrum.

Method for localized surface plasmon resonance sensing system

A wafer treating method for making adhesive dies is provided. A liquid adhesive with two-stage property is coated on a surface of a wafer. Then, the wafer is pre-cured to make the liquid adhesive transform a thermo-bonding adhesive film having B-stage property which has a glass transition temperature not less than 40&#xb0; C. for handling without adhesive under room temperature. After positioning the wafer, the wafer is singulated to form a plurality of dies with adhesive for die-to-die stacking, die-to-substrate or die-to-leadframe attaching.

Wafer treating method for making adhesive dies

A manufacturing process for chip package without core is disclosed. First of all, a conductive layer with a first surface and a second surface is provided. A first film is formed onto the first surface, and the conductive layer is patterned to form a patterned circuit layer. A solder resistance layer is formed on the patterned circuit layer and then patterned to expose parts of the patterned circuit layer. After a second film is formed on the solder resistance layer and the first film is removed, a chip is disposed on the first surface and electrically connected to the patterned circuit layer. A molding compound is formed to cover the patterned circuit layer and fix the chip onto the patterned circuit layer. After that, the second film is removed.

Manufacturing process for chip package without core

A high frequency IC package mainly includes a substrate, a bumped chip, and a plurality of conductive fillers where the substrate has a plurality of bump holes penetrating from the top surface to the bottom surface. The active surface of the chip is attached to the top surface of the substrate in a manner that the bumps are inserted into the bump holes respectively. The conductive fillers are formed in the bump holes to electrically connect the bumps to the circuit layer of the substrate. The high frequency IC package has a shorter electrical path and a thinner package thickness.

High frequency IC package and method for fabricating the same

A manufacturing method of a chip package structure is provided. A circuit substrate having a first surface, a second surface, and a through hole connecting the first surface and the second surface is provided. A chip having an active surface and bonding pads disposed on the active surface is provided. The chip is fixed on the circuit substrate, wherein the second surface is opposite to the active surface and the bonding pads are exposed to the through hole. Bonding wires connecting the bonding pads and the first surface are formed through the through hole. A film having an opening is formed on the first surface. The bonding wires, the bonding pads, the through hole, and part of the first surface are exposed by the opening. An encapsulant is formed to encapsulate part of the active surface, the bonding wires, and part of the first surface. The film is removed.

Chip package structure and manufacturing method thereof

A chip package structure includes a substrate, a chip, a first B-stage adhesive, bonding wires, a heat sink and a molding compound. The substrate comprises a first surface, a second surface and a through hole. The chip is arranged on the first surface of the substrate and electrically connected thereto while the through hole of the substrate exposes a portion of the chip. The first B-stage adhesive is arranged between the chip and the first surface of the substrate, and the chip is attached to the substrate through the first B-stage adhesive. The bonding wires are connected between the chip exposed by the through hole and second surface of the substrate. The heat sink is arranged on the first surface of the substrate, covering the chip. The molding compound is arranged on the second surface of the substrate, covering a portion of the substrate and bonding wires.

Growing community of inventors

Tainan County, Taiwan

Chun-Hung Lin