Taiwan Semiconductor Manufacturing Comp. Ltd.

Industrial Technology Research Institute

Ememory Technology Inc.

Advanced Semiconductor Engineering, Inc.

Academia Sinica

Other

Sunplus Technology Co., Ltd.

The Scripps Research Institute

Compal Electronics, Inc.

Macronix International Co., Ltd.

Inventec Corp.

Inventec (pudong) Technology Corporation

Solid State System Co., Ltd.

China Textile Institute

Sentec E&e Co., Ltd.

Chun-Hung Lin

Yu-Feng Chen

Han-Ping Pu

Kai-Chiang Wu

Ming-Da Cheng

Heng-Hsin Liu

Chin-Jyi Wu

Cheng-Da Huang

Chi-Huey Wong

Chen-Der Tsai

Chia-Chiang Chang

Hsien-Wei Chen

Ming-Che Ho

Chun-Cheng Lin

Chien-Hsun Lin

Yao-Wen Guo

Chen-Hua Douglas Yu

Chung-Shi Liu

Mirng-Ji Lii

Shy-Jay Lin

Chih-Fan Huang

Sheng-Chi Chin

Ting-Hao Hsu

Yu-Ching Lee

Li-Kong Turn

Ching-Fang Yu

Yi-Ting Chen

Shui-Tein Chen

Hong-Sen Chen

Jui-Chung Peng

Chen-Shien Chen

Chin-Hsiang Lin

Tin-Hao Kuo

Tsung-Ding Wang

Yi-Wen Wu

Chih-Hang Tung

Chun-Lin Lu

Su Tao

Tzung-Chi Fu

Chih-Wei Chen

Ming-Kai Liu

Jung Wei Cheng

Yu-min Liang

Yu-Wei Lin

Jui-Chun Peng

Ching-Hsiang Chang

Yu-Chen Hsu

Hsien-Liang Meng

Chun-Chih Chuang

Chih-Chun Chen

Hann-Tsong Wang

Hsueh-Yi Chung

Yung-Hsing Chang

Wen-Hsin Lin

Hung-Jui Kuo

Tai-Chun Huang

Chi-Hung Liao

Tsung-Shu Lin

Shih-Wei Liang

Yu-Chia Lai

Ho-Ming Tong

Jen-Kuang Fang

Ming-Yen Chiu

Chun-Chieh Chen

Huang-Chin Tang

Chun-Chi Lee

Hsien-Ming Tu

Chien-Chang Lee

Chang-Pin Huang

Yung-Chi Lee

Chia-Fu Chang

Chao-Kai Cheng

Chien-Chia Chiu

Yu-Chen Chou

Tsung-Hua Wu

Wei-Chung Wang

Chi-Chih Shen

Wei-Chung Hsiao

Gwo-Jenn Shen

Wan-Wen Chiu

Kun-Wei Lin

Shih-Kuang Chen

Chun-Hung Lu

Chieh-Yi Huang

Chih-Hung Wang

Shyh-Ing Wu

Cheng-Hsin Chen

Wen-Tung Hsu

Huan-Chi Tseng

Bor-Rung Su

Shih-Chan Huang

Lun-Chun Chen

Ping-Lung Ho

Wen-Bin Yang

Ching-Fu Horng

An-Kuo Yang

Yu-Chyi Harn

Shu-Lan Yao

Ting-Chung Hu

Jiun-Hung Chen

An antifuse-type one time programming memory cell at least includes an antifuse transistor. The antifuse transistor includes a first nanowire, a first gate structure, a first drain/source structure and a second drain/source structure. The first nanowire is surrounded by the first gate structure. The first gate structure comprises a first spacer, a second spacer, a first gate dielectric layer and a first gate layer. The first drain/source structure is electrically contacted with a first terminal of the first nanowire. The second drain/source structure is electrically contacted with a second terminal of the first nanowire.

Antifuse-type one time programming memory cell with gate-all-around transistor

A selection circuit includes a main selection circuit and an auxiliary selection circuit. When a first voltage and a second voltage are different, the main selection circuit selects a higher one of the first voltage and the second voltage as an output voltage. When the first voltage and the second voltage are equal, the auxiliary selection circuit generates the output voltage according to the first voltage and the second voltage.

PMOS voltage selection circuit with an auxiliary selection circuit to prevent a floating output

An anti-fuse memory device includes an anti-fuse module, a reference current circuit and a controller. A write enable signal enables a write controller and a write buffer of the anti-fuse module to program a selected anti-fuse memory cell in an anti-fuse array of the anti-fuse module, and a timing controller of the anti-fuse module stops a program operation of the anti-fuse array after a sense amplifier of the anti-fuse module changes a state of a readout data signal for a predetermined time duration.

Anti-fuse memory device

A chip includes a semiconductor substrate, an electrical connector over the semiconductor substrate, and a molding compound molding a lower part of the electrical connector therein. A top surface of the molding compound is lower than a top end of the electrical connector. A recess extends from the top surface of the molding compound into the molding compound.

Forming recesses in molding compound of wafer to reduce stress

A non-volatile memory cell includes a first select transistor, a first floating gate transistor, a second floating gate transistor and a second select transistor. The first select transistor is connected with a program source line and a program word line. The first floating gate transistor includes a floating gate. The first floating gate transistor is connected with the first select transistor and a program bit line. The second floating gate transistor includes a floating gate. The second floating gate transistor is connected with a read source line. The second select transistor is connected with the second floating gate transistor, the read word line and the read bit line. The floating gate of the second floating gate transistor is connected with the floating gate of the first floating gate transistor.

Non-volatile memory cell and non-volatile memory cell array

When a driving circuit of an anti-fuse memory device programs a selected anti-fuse memory cell, voltage differences between unselected bit lines and unselected anti-fuse control lines would be eliminated or decreased to an acceptable value by floating unselected anti-fuse control lines or by applying a second control line voltage to the unselected anti-fuse control lines. Leakage currents flowing from unselected bit lines through ruptured anti-fuse transistors of the anti-fuse memory device to the unselected anti-fuse control lines would be decreased or eliminated, and program disturbance would be avoided.

Anti-fuse memory device, memory array, and programming method of an anti-fuse memory device for preventing leakage current and program disturbance

An automatic device for brewing beverages at least comprises an ice cube meter, at least one beverage supply device, at least one robotic arm, a feed conveyor belt, a plurality of feeders, and a film sealing machine, mainly uses the robotic arm to take up ice cubes and a beverage from the ice cube meter and the beverage supply device with a hand-shake cup, then shake and mix, and pour the shaken and mixed beverage and ice cubes into a beverage cup, the beverage cup is conveyed to pass through the feeders by the feed conveyor belt, ingredient is squeezed into the beverage cup by the feeder, and finally the beverage cup containing the beverage, ice cubes and ingredient is conveyed by the feed conveyor belt to the film sealing machine for sealing.

Automatic device for brewing beverages

A semiconductor device includes a first semiconductor die package. The first semiconductor package includes a molding compound, and a conductive element in the molding compound, wherein a top surface of the conductive element is above or co-planar with a top-most surface of the molding compound. The semiconductor device further includes a second semiconductor die package. The second semiconductor package includes a plurality of copper-containing contacts on a single metal pad, wherein each of the plurality of copper-containing contacts is bonded to the conductive element.

Semiconductor device package including embedded conductive elements

A trace configuration calculating method is applied to pivotal connection of a first workpiece and a hinge. A first trace space is formed at a position where the hinge is pivoted to the first workpiece. A first trace is disposed through the first trace space. The trace configuration calculating method includes the hinge and the first workpiece rotating first and second angles to make the first trace space have first and second contour cross-sections respectively, overlapping the first and second contour cross-sections to form a first intersection area, calculating a first maximum inscribed circle according to the first intersection area, and determining a first optimal center and a first maximum diameter of the first trace according to the first maximum inscribed circle.

Trace configuration calculating method and portable electronic apparatus thereof

A self-biased sense amplification circuit includes a local bit line, a reset unit, a main bit lie, a pre-amplifier, a data line, a sample reference unit, and a sense amplifier. The local bit line receives a cell current generated by a memory cell during a sense operation. The reset unit resets the local bit line to a first system voltage during a sample operation. The pre-amplifier generates a read current on the main bit line according to a voltage of the local bit line during the sample operation and the sense operation. The data line is coupled to the main bit line. The sample reference unit generates a first reference current and a second reference current during the sample operation, and generates the first reference current during the sense operation. The sense amplifier senses a voltage of the data line.

Self-biased sense amplification circuit

A reference voltage generator includes an output terminal, a current source, a reference circuit, a protection circuit, and a control circuit. The output terminal outputs a reference voltage. The current source is coupled to the output terminal, and generates a reference current. The reference circuit is coupled to the output terminal, and generates a reference voltage according to the reference current. The protection circuit is coupled to the output terminal, and adjusts a voltage of the output terminal to an operating voltage. The control circuit is coupled to the reference circuit and the protection circuit. The control circuit controls the reference circuit and the protection circuit according to a start signal.

Reference voltage generator capable of reducing hot carrier stress

A non-volatile memory includes a memory cell array, an amplifying circuit and a first multiplexer. The memory cell array includes m&#xd7;n memory cells. The memory cell array is connected with a control line, m word lines and n local bit lines, wherein m and n are positive integers. The amplifying circuit includes n sensing elements. The n sensing elements are respectively connected between the n local bit lines and n read bit lines. The first multiplexer is connected with the n local bit lines and the n read bit lines. According to a first select signal, the first multiplexer selects one of the n local bit lines to be connected with a first main bit line and selects one of the n read bit lines to be connected with a first main read bit line.

Non-volatile memory and memory sector thereof

A memory system includes a plurality of memory cells. A memory cell includes an anti-fuse transistor, a first select unit, and a second select unit. The anti-fuse transistor has a first terminal, a second terminal, and a control terminal coupled to an anti-fuse control line. The first select unit is coupled to the first terminal of the anti-fuse transistor, a first bit line, and an odd word line. The second select unit is coupled to the second terminal of the anti-fuse transistor, a second bit line, and an even word line. During a pre-screen operation of the memory cell, the odd word line and the even word line are at different voltages.

Memory system capable of pre-screening internal transistors

A random bit cell includes a random bit cell. The random bit cell includes a volatile memory unit, a first non-volatile memory unit, a second non-volatile memory unit, a first select transistor, and a second select transistor. The first non-volatile memory unit is coupled to a first data terminal of the volatile memory unit, and the second non-volatile memory unit is coupled to a second data terminal of the volatile memory unit. The first select transistor has a first terminal coupled to the first data terminal of the volatile memory unit, a second terminal coupled to a first bit line, and a control terminal coupled to a word line. The second select transistor has a first terminal coupled to the second data terminal of the volatile memory unit, a second terminal coupled to a second bit line, and a control terminal coupled to a word line.

Random bit cell with memory units

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Taipei, Taiwan

Chun-Hung Lin