Chartered Semiconductor Manufacturing Ltd (corporation)

Globalfoundries Singapore Pte. Ltd.

International Business Machines Corporation

Chun Hui Low

Soh Yun Siah

Eng Hua Lim

Chong Wee Lim

Sang Yee Loong

Kong Hean Lee

Hong Lim Lee

Qiang Guo

Liang Choo Hsia

Bei Chao Zhang

Timothy Joseph Dalton

Mei Sheng Zhou

Huang Liu

Yelehanka Ramachandramurthy Pradeep

Nicholas C M Fuller

Wei Lu

Kin Leong Pey

Hai Cong

Chim Seng Seet

Alex K H See

Raymond Joy

Beichao Zhang

Jianhui Ye

Yi-hsiung Lin

Kong-Hean Lee

Yan Shan Li

A composite etch stop layer which comprises primary and secondary stop layers is used to form contacts in a dielectric layer to contact regions in a substrate. The secondary etch stop layer includes a high-k dielectric material to achieve high etch selectivity with the dielectric layer during contact formation. The secondary stop layer is removed to expose the contact regions. Removal of the secondary stop layer is achieved with high selectivity to the materials therebelow.

Method of forming high-k dielectric stop layer for contact hole opening

Test structures including test trenches are used to define critical dimension of trenches in a via level of an integrated circuit to produce substantially the same depth. The trenches are formed at the periphery of the IC to serve as guard rings.

Critical dimension for trench and vias

An integration approach to improve electromigration resistance in a semiconductor device is described. A via hole is formed in a stack that includes an upper dielectric layer, a middle TiN ARC, and a lower first metal layer and is filled with a conformal diffusion barrier layer and a second metal layer. A key feature is that the etch process can be selected to vary the shape and location of the via bottom. A round or partially rounded bottom is formed in the first metal layer to reduce mechanical stress near the diffusion barrier layer. On the other hand, a flat bottom which stops on or in the TiN ARC is selected when exposure of the first metal layer to subsequent processing steps is a primary concern. Electromigration resistance is found to be lower than for a via structure with a flat bottom formed in a first metal layer.

Via electromigration improvement by changing the via bottom geometric profile

Methods of forming a metal line and/or via critical dimension (CD) in a single or dual damascene process on a semiconductor substrate, and the resist scheme implemented, are disclosed. The method includes forming a multiple layer resist scheme including a first planarizing layer of a first type material over the substrate, a second dielectric layer of a second type material over the planarizing layer, and a third photoresist layer of a third type material over the dielectric layer. The types of material alternate between organic and inorganic material. The third layer is patterned for the metal line and/or via CD. Sequential etching to form the metal line and/or via critical dimension using a tailored etch recipe particular to each of the first photoresist layer, the second dielectric layer and the third planarizing layer as each layer is exposed is then used. Accurate CD formation and adequate resist budget are provided.

Multiple layer resist scheme implementing etch recipe particular to each layer

An improved and new process for fabricating MOSFET's in shallow trench isolation (STI), with sub-quarter micron ground rules, includes a passivating trench cap layer of silicon nitride. The silicon nitride passivating trench cap is utilized in the formation of borderless or &ldquo;unframed&rdquo; electrical contacts, without reducing the poly to poly spacing. Borderless contacts are formed, wherein contact openings are etched in an interlevel dielectric (ILD) layer over both an active region (P-N junction) and an inactive trench isolation region. During the contact hole opening, a selective etch process is utilized which etches the ILD layer, while the protecting passivating silicon nitride trench cap layer remains intact protecting the P-N junction at the edge of trench region. Subsequent processing of conductive tungsten metal plugs are prevented from shorting by the passivating trench cap. This method of forming borderless contacts with a passivating trench cap in a partially recessed trench isolation scheme improves device reliability since it prevents electrically short circuiting of the P-N junction and lowers the overall diode leakage. Furthermore, the use of the silicon nitride trench cap protects the underlying STI trench oxide during subsequent cleaning process steps. In addition, the nitride cap protects the STI oxide from excessive recess formation and prevents the exposure of STI seams, in addition to minimizing transistor junction leakage.

Silicon nitride capped shallow trench isolation method for fabricating sub-micron devices with borderless contacts

A new method is established to form different silicide layers over the top of the gate electrode and the surface of the source/drain regions. A thin layer of TiSi,is formed over the source/drain regions by depositing a layer of titanium and annealing this layer with the silicon substrate. The gate electrode is created as a recessed electrode, in the top recession of the electrode a layer of CoSi,is formed by depositing a layer of cobalt over the gate electrode. This layer of COSi,serves as the electrical gate contact point.

Optimized Co/Ti-salicide scheme for shallow junction deep sub-micron device fabrication

An improved and new process for fabricating MOSFET's in shallow trench isolation (STI), with sub-quarter micron ground rules, includes a passivating trench liner of silicon nitride. The silicon nitride passivating liner is utilized in the formation of borderless or &ldquo;unframed&rdquo; electrical contacts, without reducing the poly to poly spacing. Borderless contacts are formed, wherein contact openings are etched in an interlevel dielectric (ILD) layer over both an active region (P-N junction) and an inactive trench isolation region. During the contact hole opening, a selective etch process is utilized which etches the ILD layer, while the protecting passivating silicon nitride liner remains intact protecting the P-N junction at the edge of trench region. Subsequent processing of conductive tungsten metal plugs are prevented from shorting by the passivating trench liner. This method of forming borderless contacts with a passivating trench liner in a partially recessed trench isolation scheme improves device reliability since it prevents electrically short circuiting of the P-N junction and lowers the overall diode leakage. In addition, the use of this invention's semi-recessed STI process scheme helps to reduce the aspect ratio of the trench, thereby aiding the filling of the trench. Therefore, with the process described herein, STI oxide seam formation is eliminated.

Partially recessed shallow trench isolation method for fabricating borderless contacts

A method of fabricating shallow trench isolations has been achieved. A semiconductor substrate is provided. A pad oxide layer is grown overlying the semiconductor substrate. A silicon nitride layer is deposited. The silicon nitride layer and the pad oxide layer are patterned to form a hard mask. The openings in the hard mask correspond to planned trenches in the semiconductor substrate. A silicon dioxide layer is deposited overlying the silicon nitride layer and the semiconductor substrate. The silicon dioxide layer is anisotropically etched to form sidewall spacers on the inside of the openings of the hard mask. The semiconductor substrate is etched to form the trenches. The sidewall spacers are etched away. The semiconductor substrate is sputter etched to round the corners of the trenches. An oxide trench lining layer is grown overlying the semiconductor substrate. A trench fill layer is deposited overlying the silicon nitride layer and filling the trenches. The trench fill layer is polished down to the top surface of the silicon nitride layer. The silicon nitride layer is etched away. The trench fill layer and the pad oxide layer are polished down to the top surface of the semiconductor substrate to complete the shallow trench isolation, and the integrated circuit device is completed.

Method to form shallow trench isolations with rounded corners and reduced trench oxide recess

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Johor, Malaysia

Chun Hui Low