National Taiwan Normal University

Industrial Technology Research Institute

Phison Electronics Corporation

Chun-Hu Cheng

Chun-Yen Chang

Yu-Chien Chiu

Wei Hung Lin

Ya-Wen Chou

Yu-Li Lin

Hsiao-Hsuan Hsu

Chien Liu

A storage memory device includes a vertical field effect transistor including a semiconductor substrate; a pillar extending upwardly from the substrate and containing a source, a drain, and a channel disposed therebetween; a first insulating layer surrounding the channel; a stacked structure surrounding the first insulating layer; and a gate unit. The stacked structure includes a charge trapping layer and a composite element. The composite element includes a ferroelectric layer made of a doped hafnium oxide-based material that has a predominantly orthorhombic phase and exhibits a negative capacitance; and an antiferroelectric layer made of a zirconium oxide-based material that has a predominantly tetragonal phase.

Storage memory device

A flash memory structure and a method of making the same are provided. The flash memory structure comprises a substrate, a source, a drain, a tunnel isolation layer, a ferroelectric-charge-trapping layer, at least one blocking isolation layer and at least one gate. The substrate is made of a semiconductive material. The source is formed on the substrate. The drain is formed on the substrate and spaced apart from the source. The tunnel isolation layer is formed on the substrate. The ferroelectric-charge-trapping layer is formed on the tunnel isolation layer and contains a charge-trapping layer and a ferroelectric negative-capacitance effect layer. The at least one blocking isolation layer is formed on the ferroelectric-charge-trapping layer. The at least one gate is formed on the blocking isolation layer. The ferroelectric negative-capacitance effect layer is made of a material with the ferroelectric negative-capacitance effect.

Flash memory structure and method of manufacturing the same

A semiconductor device includes a substrate, a channel layer, a barrier layer, a source and a drain, a p-type nitride layer and a strain gate. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The source and the drain are respectively disposed at two sides of the barrier layer. The p-type nitride layer is disposed on the barrier layer. The strain gate is disposed over the p-type nitride layer for tuning a first strain of the channel layer and a second strain of the barrier layer.

Semiconductor device and method of manufacturing the same

A three-dimensional non-volatile memory structure including a substrate, a stacked structure, a charge storage pillar, a channel pillar, and a ferroelectric material pillar is provided. The stacked structure is disposed on the substrate and includes a plurality of conductive layers and a plurality of first dielectric layers, and the conductive layers and the first dielectric layers are alternately stacked. The charge storage pillar is disposed in the stacked structure. The channel pillar is disposed inside the charge storage pillar. The ferroelectric material pillar is disposed inside the channel pillar.

Three-dimensional non-volatile memory structure and manufacturing method thereof

The disclosure provides a thermoelectric conversion structure and its use in heat dissipation device. The thermoelectric conversion structure includes a thermoelectric element, a first electrode and an electrically conductive heat-blocking layer. The thermoelectric element includes a first end and a second end opposite to each other. The first electrode is located at the first end of the thermoelectric element. The electrically conductive heat-blocking layer is between the thermoelectric element and the first electrode.

Growing community of inventors

Tainan, Taiwan

Chun-Hu Cheng