United Microelectronics Corp.

Taiwan Semiconductor Manufacturing Comp. Ltd.

Promd Biotech Co., Ltd.

Chun-Hsien Huang

Yu-Tse Kuo

Shu-Ru Wang

Chun-Yen Tseng

Wei-Jung Lin

Ching-Cheng Lung

Chih-Wei Chang

Li-Ping Huang

Chia-Wei Huang

Ming-Hsing Tsai

Chang-Hung Chen

Yu-Hung Lin

Yu-Kai Chen

Ming-Jui Chen

Ken-Yu Chang

Chih-wei Chang

Hong-Mao Lee

Hsin-Chih Yu

Chun-I Tsai

Yi-Ting Wu

Keng-Chu Lin

Sung-Li Wang

Shuen-Shin Liang

Chia-Hung Chu

Hsu-Kai Chang

Hung-Yi Huang

Hsien-Lung Yang

Ya-Lan Chiou

I-Tseng Chen

Pin-Wen Chen

Shu-Wei Yeh

Meng-Ping Chuang

Yu-Shiuan Wang

Chang-Ting Chung

Yee-Chia Yeo

Huicheng Chang

Liang-Yin Chen

Su-Hao Liu

Chien-Hung Zordius Chen

Kuo-Ju Chen

Hsin-Yu Chen

Hung-Hsu Chen

Min-Hsiu Hung

Yung-Feng Cheng

Ya-Yi Cheng

Yi-Hsiang Chao

Hung-Chang Hsu

Yu-Shiang Yang

Chih-Wei Tsai

I-Li Chen

Kai-Lin Chuang

Yuan-Chen Hsu

Wei-Cheng Lin

Yi-Wei Chen

Ching-Wen Hung

Shih-Fang Tzou

Chih-Sen Huang

Li-Wei Chu

Hon-Lin Huang

Chen-Yuan Kao

Sheng-Hsuan Lin

Wei-Yip Loh

Yan-Ming Tsai

Chia-Han Lai

Jen-Yu Wang

Chien Chang

Chun-Chieh Chang

Te-Hung Wu

Yu-Ming Huang

Ting-Cheng Tseng

Yu-Wen Cheng

Shih-Chun Tsai

Kai-Chieh Yang

Koji Nii

Chien-Hung Chen

Ssu-I Fu

Shih-Hung Tsai

Chih-Kai Hsu

Yu-Hsiang Hung

Jyh-Shyang Jenq

Cheng-Tung Huang

Yuichiro Ishii

Jia-Rong Wu

Peng-Fu Hsu

Ching-Yi Chen

Chih-Hsien Tang

Po-Chun Yang

Yung-Ching Hsieh

Jian-Jhong Chen

Wei-Chih Su

Wei-Chi Lee

Yao-Jen Fan

Chen-Wei Lee

Shih-Hao Liang

Bo-Chang Li

Han-Tsun Wang

Kevin Lee

Jhen-Siang Wu

Hong-Ming Wu

Pei-Wen Wu

A pre-cleaning technique described herein may be used to remove native oxides and/or other contaminants from a semiconductor device in a manner in which the likelihood of chopping, clipping, and/or sidewall spacer thickness reduction is reduced. As described herein, a protection layer is formed on a capping layer over a gate structure of a transistor. A pre-cleaning operation is then performed to remove native oxides from the top surface of a source/drain region of the transistor. In the pre-cleaning operation, the protection layer is consumed instead of the material of the capping layer. In this way, the use of the protection layer reduces the likelihood of removal of material from the capping layer and/or reduces the amount of material that is removed from the capping layer during the pre-cleaning operation.

Semiconductor device pre-cleaning

A method includes forming a dielectric layer over a source/drain region. An opening is formed in the dielectric layer. The opening exposes a portion of the source/drain region. A conductive liner is formed on sidewalls and a bottom of the opening. A surface modification process is performed on an exposed surface of the conductive liner. The surface modification process forms a surface coating layer over the conductive liner. The surface coating layer is removed to expose the conductive liner. The conductive liner is removed from the sidewalls of the opening. The opening is filled with a conductive material in a bottom-up manner. The conductive material is in physical contact with a remaining portion of the conductive liner and the dielectric layer.

Contact features of semiconductor device and method of forming same

A method includes depositing an inter-layer dielectric (ILD) over a source/drain region; forming a contact opening through the ILD, wherein the contact opening exposes the source/drain region; forming a metal-semiconductor alloy region on the source/drain region; depositing a first layer of a conductive material on the metal-semiconductor alloy region; depositing an isolation material along sidewalls of the contact opening and over the first layer of the conductive material; etching the isolation material to expose the first layer of the conductive material, wherein the isolation material extends along sidewalls of the contact opening after etching the isolation material; and depositing a second layer of the conductive material on the first layer of the conductive material.

Transistor source/drain contacts and methods of forming the same

Some implementations described herein provide a gas curtain system. The gas curtain system includes various components to prevent a gas flowing within a chamber of an interface tool from flowing through an opening into a transport carrier adjacent to the interface tool. The gas curtain system may include a gas distribution component along an edge of the opening that generates a flow of another gas across the opening towards an opposite edge of the opening. In this way, the gas from the chamber is prevented from entering the transport carrier. By preventing the gas from the chamber from entering the transport carrier, a relative humidity within an environment of the transport carrier is maintained such that condensation of moisture on one or more semiconductor wafers within the transport carrier is mitigated.

Interface tool and methods of operation

A layout pattern of a magnetoresistive random access memory (MRAM) includes a substrate having a first cell region and a second cell region and a diffusion region on the substrate extending through the first cell region and the second cell region. Preferably, the diffusion region includes a first H-shape and a second H-shape according to a top view.

Layout pattern of magnetoresistive random access memory

The present invention provides a spin-orbit torque magnetic random access memory (SOT-MRAM) circuit, including a read transistor pair with two read transistors in parallel, a write transistor pair with two write transistors in parallel, a SOT memory cell with a magnetic tunnel junction (MTJ) and a SOT layer, wherein one end of the MTJ is connected to the source of the read transistor pair and the other end of the MTJ is connected to the SOT layer, and one end of the SOT layer is connected to a source line and the other of the SOT layer is connected to the source of the write transistor pair, a read bit line is connected to the drain of the read transistor pair and a write bit line is connected to the drain of the read transistor.

Spin-orbit torque magnetic random access memory circuit and layout thereof

A method includes forming a first metallic feature, forming a dielectric layer over the first metallic feature, etching the dielectric layer to form an opening, with a top surface of the first metallic feature being exposed through the opening, and performing a first treatment on the top surface of the first metallic feature. The first treatment is performed through the opening, and the first treatment is performed using a first process gas. After the first treatment, a second treatment is performed through the opening, and the second treatment is performed using a second process gas different from the first process gas. A second metallic feature is deposited in the opening.

Phase control in contact formation

A method includes forming a dielectric layer over an epitaxial source/drain region. An opening is formed in the dielectric layer. The opening exposes a portion of the epitaxial source/drain region. A barrier layer is formed on a sidewall and a bottom of the opening. An oxidation process is performing on the sidewall and the bottom of the opening. The oxidation process transforms a portion of the barrier layer into an oxidized barrier layer and transforms a portion of the dielectric layer adjacent to the oxidized barrier layer into a liner layer. The oxidized barrier layer is removed. The opening is filled with a conductive material in a bottom-up manner. The conductive material is in physical contact with the liner layer.

A method of fabricating a contact structure includes the following steps. An opening is formed in a dielectric layer. A conductive material layer is formed within the opening and on the dielectric layer, wherein the conductive material layer includes a bottom section having a first thickness and a top section having a second thickness, the second thickness is greater than the first thickness. A first treatment is performed on the conductive material layer to form a first oxide layer on the bottom section and on the top section of the conductive material layer. A second treatment is performed to remove at least portions of the first oxide layer and at least portions of the conductive material layer, wherein after performing the second treatment, the bottom section and the top section of the conductive material layer have substantially equal thickness.

Method of fabricating contact structure

The invention provides a layout pattern of static random access memory (SRAM), which at least comprises a plurality of gate structures located on a substrate and spanning the plurality of fin structures to form a plurality of transistors distributed on the substrate, wherein the plurality of transistors comprise two pull-up transistors (PU), two pull-down transistors (PD) to form a latch circuit, and two access transistors (PG) connected to the latch circuit. In each SRAM memory cell, the fin structure included in the pull-up transistor (PU) is defined as a PU fin structure, the fin structure included in the pull-down transistor (PD) is defined as a PD fin structure, and the fin structure included in the access transistor (PG) is defined as a PG fin structure, wherein a width of the PD fin structure is wider than a width of the PG fin structure.

Layout pattern of static random access memory and the forming method thereof

A semiconductor device is disclosed. The device includes a source/drain feature formed over a substrate. A dielectric layer formed over the source/drain feature. A contact trench formed through the dielectric layer to expose the source/drain feature. A titanium nitride (TiN) layer deposited in the contact trench and a cobalt layer deposited over the TiN layer in the contact trench.

Method of forming contact metal

The present invention provides a layout pattern of static random access memory, comprising a PU(first pull-up transistor), a PU(second pull-up transistor), a PDA (first pull-down transistor), a PDB (second pull-down transistor), a PDA (third pull-down transistor), a PDB (fourth pull-down transistor), a PGA (first access transistor), a PGB (second access transistor), a PGA (third access transistor) and a PGB (fourth access transistor) located on the substrate. The PDA and the PDB are connected in parallel with each other, the PDA and the PDB are connected in parallel with each other, wherein the gate structures include a first J-shaped gate structure, and the first J-shaped gate structure is an integrally formed structure.

Layout pattern of static random access memory

The present disclosure describes a method for forming capping layers configured to prevent the migration of out-diffused cobalt atoms into upper metallization layers In some embodiments, the method includes depositing a cobalt diffusion barrier layer on a liner-free conductive structure that includes ruthenium, where depositing the cobalt diffusion barrier layer includes forming the cobalt diffusion barrier layer self-aligned to the liner-free conductive structure. The method also includes depositing, on the cobalt diffusion barrier layer, a stack with an etch stop layer and dielectric layer, and forming an opening in the stack to expose the cobalt diffusion barrier layer. Finally, the method includes forming a conductive structure on the cobalt diffusion barrier layer.

Capping layer for liner-free conductive structures

Generally, examples are provided relating to conductive features that include a barrier layer, and to methods thereof. In an embodiment, a metal layer is deposited in an opening through a dielectric layer(s) to a source/drain region. The metal layer is along the source/drain region and along a sidewall of the dielectric layer(s) that at least partially defines the opening. The metal layer is nitrided, which includes performing a multiple plasma process that includes at least one directional-dependent plasma process. A portion of the metal layer remains un-nitrided by the multiple plasma process. A silicide region is formed, which includes reacting the un-nitrided portion of the metal layer with a portion of the source/drain region. A conductive material is disposed in the opening on the nitrided portions of the metal layer.

Conductive feature formation and structure

Growing community of inventors

Tainan, Taiwan

Chun-Hsien Huang