A-sat Corporation

Ubotic Company Limited

Asm Technology Singapore Pte Ltd

Other

Utac Headquarters Pte. Ltd.

Utac Hong Kong Limited

Chun Ho Fan

Neil McLellan

Kwok Cheung Tsang

Kin Pui Kwan

Wing Him Lau

Mohan Kirloskar

Ming Wang Sze

Geraldine Tsui Yee Lin

Sadak Thamby Labeeb

Tsui Yee Lin

Edward G Combs

Wing Keung Lam

Robert P Sheppard

Tak Sang Yeung

William Lap Keung Chow

Shuk Man Wong

Ed A Varga

Tai Wai Pun

Shui Ming Tse

Neil Robert McLellen

Walter De Munnik

Joseph Andrew Martin

Teng Hock Kuah

Neil Robert McLellan

Neil Mclellan

Chow Lap Keung

Kin Yan Tsang

Tsang Kwok Cheung

Ping Sheung Lau

Kin Pul Kwan

Lap Keung Chow

Hau Wan Ng

Pik Ling Lau

Emily Shui Ming Tse

Kenneth Kwan

Hoi Chi Wong

Janet Wong

Hau Wang Ng

Man Chung Chan

John Ping Sheung Lau

During the manufacture of a semiconductor package, a semiconductor wafer including a plurality of bond pads on a surface of the wafer is provided and the surface of the wafer is covered with a dielectric material to form a dielectric layer over the bond pads. Portions of the dielectric layer corresponding to positions of the bond pads are removed to form a plurality of wells, wherein each well is configured to form a through-hole between top and bottom surfaces of the dielectric layer for exposing each bond pad. A conductive material is then deposited into the wells to form a conductive layer between the bond pads and a top surface of the dielectric layer. Thereafter, the semiconductor wafer is singulated to form a plurality of semiconductor packages.

Method for manufacturing wafer-level semiconductor packages

A cavity package is set forth along with a method of manufacturing thereof. The method comprises applying a selective plating resist to a metallic substrate in a pattern to expose portions for a ring, tie bars, die attach pad and input/output wire bonding pads; elective depositing of metal plating using the selective plating resist; removing the selective metal plating resist; applying a selective etching resist to the substrate; selectively etching portions of the substrate not covered by the selective etching resist; stripping away the selective etching resist; pre-molding a leadframe to the substrate so as to surround the die attach pad portion; etching the tie bars away from the bottom surface of the substrate; attaching a semiconductor device die to the die attach pad; wire bonding the semiconductor device to the input/output wire bonding pads; and attaching a cap to the ring portion of the substrate and the die attach pad to protect the wire bonded semiconductor device die and permit electrical grounding.

Cavity package with pre-molded substrate

A cavity package is provided. The package can include a metal leadframe and a substrate attached to an interposer formed as part of the leadframe. The substrate typically has a coefficient of thermal expansion matched to the coefficient of thermal expansion of a semiconductor device to be affixed to the substrate. The semiconductor device is typically attached to an exposed top surface of the substrate. The cavity package also includes a plastic portion molded to the leadframe forming a substrate cavity. The substrate cavity allows access to the exposed top surface of the substrate for affixing the semiconductor device. The cavity package also include a connective element for grounding a lid through an electrical path from the lid to the interposer.

Cavity package with die attach pad

A cavity package is disclosed comprising a metal leadframe, a metal ring connected to the metal leadframe, a plastic body molded to the metal leadframe forming a substrate cavity including an exposed die attach pad of the leadframe for affixing a semiconductor device, exposed lead fingers of the leadframe for wire bonding to the semiconductor device and an external circuit, and an exposed top surface of the metal ring, and a metal cap for closing and encapsulating the substrate cavity. The metal ring is integrated into the pre-molded cavity leadframe for providing an electrical ground path from the metal cap to the die attach pad and permitting attachment of the metal cap to the pre-molded leadframe using solder reflow.

Cavity package with pre-molded cavity leadframe

A process for fabricating an integrated circuit package includes selectively etching a leadframe strip to define a die attach pad and a plurality of contact pads. At least one side of the die attach pad has a plurality of spaced apart pad portions. A semiconductor die is mounted to the die attach pad and wires are bonded from the semiconductor die to respective ones of the contact pads. A first surface of the leadframe strip, including the semiconductor die and wire bonds, is encapsulated in a molding material such that at least one surface of the leadframe strip is exposed. The integrated circuit package is singulated from a remainder of the leadframe strip.

Method of fabricating an integrated circuit (IC) package having a plurality of spaced apart pad portion

Disclosed is a device for holding a plurality of semiconductor devices during thermocompression bonding, comprising: a body; a plurality of support surfaces at a first side of the body, each support surface being configured for holding at least one semiconductor device during thermocompression bonding; and a plurality of internal conduits within the body, each internal conduit extending from an opening of a respective one of the support surfaces at the first side of the body to an opening at a second side of the body. In particular, the openings at the second side of the body are configured to be connected to separate pneumatic paths to be in fluid communication therewith, each pneumatic path having an independently controlled pneumatic suction force so that the openings of the support surfaces at the first side of the body are operative to selectively hold the one or more semiconductor devices against the support surfaces at the first side of the body or to release the same therefrom. An apparatus for holding semiconductor devices during thermocompression bonding, and a method of bonding a plurality of semiconductor devices to a substrate via thermocompression bonding are also disclosed.

Device for holding multiple semiconductor devices during thermocompression bonding and method of bonding

An integrated circuit package having a selectively etched leadframe strip defining a die attach pad and a plurality of contact pads, at least one side of the die attach pad having a plurality of spaced apart pad portions; a semiconductor die mounted to the die attach pad and wires bonding the semiconductor die to respective ones of the contact pads; a first surface of the leadframe strip, including the semiconductor die and wire bonds, encapsulated in a molding material such that at least one surface of the leadframe strip is exposed, and wherein solder paste is disposed on said contact pads and said at least one side of said die attach pad.

Integrated circuit package having a plurality of spaced apart pad portions

A process for fabricating a leadless plastic chip carrier. A first surface of a leadframe strip is selectively etched to thereby provide depressions in the first surface and metal contacts are deposited in the depressions in the first surface of the leadframe strip. At least one layer of metal is selectively plated on at least the metal contacts to provide a plurality of selectively plated contact pads and a die attach pad. A semiconductor die is mounted on the first surface of the die attach pad and the semiconductor die is wire bonded to ones of the contact pads. The wire bonds and the semiconductor die are encapsulated in a molding material such that the molding material covers the die attach pad and the contact pads. The leadframe strip is etched away thereby exposing the metal contacts in the form of an array and the leadless plastic chip carrier is singulated from other leadless plastic chip carriers.

Leadless plastic chip carrier with contact standoff

A process for fabricating an integrated circuit package includes establishing a plating mask on a first surface of a metal carrier. The plating mask defines a plurality of components including a die attach pad, at least one row of contact pads and at least one additional electronic component. A plurality of metallic layers is deposited on exposed portions of the first surface of the metal carrier. The plating mask is stripped from the metal carrier, leaving the plurality of metallic layers in the form of the plurality of components. A semiconductor die is mounted to die attach pad and pads of the semiconductor die are electrically connected to ones of the contact pads and to the additional electronic component. The first surface of the metal carrier is overmolded to encapsulate the plurality of components and the semiconductor die and the metal carrier is etched away.

Electronic components such as thin array plastic packages and process for fabricating same

A method of fabricating an integrated circuit package. The method includes providing a first leadframe and a second leadframe, laminating the second leadframe to a portion of the first leadframe in order to create a multi-layer laminated leadframe, and mounting a semiconductor die on another portion of the first leadframe.

Multiple leadframe laminated IC package

An integrated circuit package is provided. The package includes a substrate having first and second surfaces and a plurality of conductive traces therebetween. The substrate further has a cavity therein and a heat slug is fixed to the substrate and spans the cavity. A semiconductor die is mounted to the heat slug such that at least a portion of the semiconductor die is disposed in the cavity. A plurality of wire bonds connect the semiconductor die to ones of the conductive traces of the substrate and an encapsulating material encapsulates the wire bonds and the semiconductor die. A ball grid array is disposed on the first surface of the substrate. Bumps of the ball grid array are in electrical connection with ones of the conductive traces.

Thin ball grid array package

A process for fabricating an integrated circuit package includes: selectively etching a leadframe strip to define a die attach pad and at least one row of contact pads; mounting a semiconductor die to one side of the leadframe strip, on the die attach pad; wire bonding the semiconductor die to ones of the contact pads; releasably clamping the leadframe strip in a mold by releasably clamping the contact pads; molding in a molding compound to cover the semiconductor die, the wire bonds and a portion of the contact pads not covered by the clamping; releasing the leadframe strip from the mold; depositing a plurality of external contacts on the one side of the leadframe strip, on the contact pads, such that the external contacts protrude from the molding compound; mounting at least one of an active and a passive component to a second side of said leadframe strip; and singulating to provide the integrated circuit package.

Integrated circuit package with partially exposed contact pads and process for fabricating the same

Growing community of inventors

Hong Kong, China

Chun Ho Fan