Taiwan Semiconductor Manufacturing Comp. Ltd.

Chun-Feng Nieh

Huicheng Chang

Yu-Chang Lin

Tien-Shun Chang

Tsan-Chun Wang

Yee-Chia Yeo

Hou-Yu Chen

Chiao-Ting Tai

Li-Ting Wang

Tze-Liang Lee

Chien-Hao Chen

Yong-Yan Lu

Keh-Chiang Ku

Hung-Ta Lin

Hsin-Wei Wu

Tsun-Jen Chan

Hsun Chang

Che-Fu Chiu

Shih-Chang Chen

Chung-Yi Yu

Li-Te S Lin

Chii-Ming M Wu

Han-Ting Tsai

Ming-Huan Tsai

Yimin Huang

Chun-Fai Cheng

Wei-Ting Chien

Sih-Jie Liu

Chih-Pin Tsao

Wei-Han Fan

Hou-Ju Li

Wen-Tai Lu

Bau-Ming Wang

Szu-Ying Chen

Liang-Yin Chen

Hsueh-Chang Sung

Pang-Yen Tsai

Tsz-Mei Kwok

Chi-Ming Chen

Kuan-Yu Chen

Chien-Chang Su

Nai-Han Cheng

Hsien-Hsin Lin

Chi-Chun Chen

Sen-Hong Syue

Ching-Yi Chen

Li-Ping Huang

Huang-Ming Chen

Wei-Yen Woon

Hsing-Jui Lee

Pei-Chao Su

Chih-Chiang Wang

Chung-Ru Yang

Jyun-Hao Lin

Yu-Chen Su

Chun Hsiung Tsai

Chun-Sheng Liang

Chia-Cheng Chen

Da-Wen Lin

Jeff J Xu

Wan-Yi Kao

Chun-Hsiung Tsai

Chien-Tai Chan

Chia-Ling Chan

Mong Song Liang

Haiting Wang

Fung Ka Hing

Shih-Hsiang Chiu

Wen-Li Chiu

Mao-Rong Yeh

Karen Mai

Yu-Chi Fu

Chong-Wai Lo

Keh-Chiang Kuo

Yu Chi-Fu

A semiconductor device and a method of forming the same are provided. The method includes forming a semiconductor fin extending from a substrate. A dummy gate stack is formed over the semiconductor fin. The dummy gate stack extends along sidewalls and a top surface of the semiconductor fin. The semiconductor fin is patterned to form a recess in the semiconductor fin. A semiconductor material is deposited in the recess. An implantation process is performed on the semiconductor material. The implantation process includes implanting first implants into the semiconductor material and implanting second implants into the semiconductor material. The first implants have a first implantation energy. The second implants have a second implantation energy different from the first implantation energy.

Method of manufacturing a source/drain of a semiconductor device using multiple implantation processes

A method of transferring semiconductor wafers and a semiconductor wafer support device including lift pins having a first end configured to contact a backside surface of the semiconductor wafer and at least one stress reduction feature. The stress reduction feature may be configured to reduce contact stress between the lift pins and the wafer.

Method and device to reduce epitaxial defects due to contact stress upon a semicondcutor wafer

A nanoFET transistor includes doped channel junctions at either end of a channel region for one or more nanosheets of the nanoFET transistor. The channel junctions are formed by a iterative recessing and implanting process which is performed as recesses are made for the source/drain regions. The implanted doped channel junctions can be controlled to achieve a desired lateral straggling of the doped channel junctions.

Ion implantation of nanostructures for nano-FET

A semiconductor device and method of manufacture are provided. In some embodiments a divergent ion beam is utilized to implant ions into a capping layer, wherein the capping layer is located over a first metal layer, a dielectric layer, and an interfacial layer over a semiconductor fin. The ions are then driven from the capping layer into one or more of the first metal layer, the dielectric layer, and the interfacial layer.

Gate structure of semiconductor device and method of manufacture

A semiconductor device may include a semiconductor fin, a source/drain region extending from the semiconductor fin, and a gate electrode over the semiconductor fin. The semiconductor fin may include a first well and a channel region over the first well. The first well may have a first dopant at a first dopant concentration and the channel region may have the first dopant at a second dopant concentration smaller than the first dopant concentration. The first dopant concentration may be in range from 10atoms/cmto 10atoms/cm.

Semiconductor device having a doped fin well

A FinFET is provided including a channel region containing a constituent element and excess atoms, the constituent element belonging to a group of the periodic table of elements, wherein said excess atoms are nitrogen, or belong to said group of the periodic table of elements, and a concentration of said excess atoms in the channel region is in the range between about 1019 cm−3 and about 1020 cm−3.

Semiconductor device with implant and method of manufacturing same

A semiconductor device includes a substrate, a fin structure and an isolation layer formed on the substrate and adjacent to the fin structure. The semiconductor device includes a gate structure formed on at least a portion of the fin structure and the isolation layer. The semiconductor device includes an epitaxial layer including a strained material that provides stress to a channel region of the fin structure. The epitaxial layer has a first region and a second region, in which the first region has a first doping concentration of a first doping agent and the second region has a second doping concentration of a second doping agent. The first doping concentration is greater than the second doping concentration. The epitaxial layer is doped by ion implantation using phosphorous dimer.

Enhanced channel strain to reduce contact resistance in NMOS FET devices

A manufacturing method of a semiconductor device, comprises the following steps: providing a semiconductor substrate; forming a dummy insulation layer and a dummy electrode sequentially stacked on the semiconductor substrate; forming spacers on sidewalls of the dummy electrode; removing the dummy electrode to exposes inner sidewalls of the spacers; and performing an ion implantation process to the inner sidewalls of the spacers and the dummy insulation layer.

Semiconductor device and manufacturing method thereof

A method of forming a semiconductor device includes performing a first implantation process on a semiconductor substrate to form a deep p-well region, performing a second implantation process on the semiconductor substrate with a diffusion-retarding element to form a co-implantation region, and performing a third implantation process on the semiconductor substrate to form a shallow p-well region over the deep p-well region. The co-implantation region is spaced apart from a top surface of the semiconductor substrate by a portion of the shallow p-well region, and the dee p-well region and the shallow p-well region are joined with each other. An n-type Fin Field-Effect Transistor (FinFET) is formed, with the deep p-well region and the shallow p-well region acting as a well region of the n-type FinFET.

Reduce well dopant loss in FinFETs through co-implantation

A method includes forming a source/drain region in a semiconductor fin; after forming the source/drain region, implanting first impurities into the source/drain region; and after implanting the first impurities, implanting second impurities into the source/drain region. The first impurities have a lower formation enthalpy than the second impurities. The method further includes after implanting the second impurities, annealing the source/drain region.

Dual dopant source/drain regions and methods of forming same

Ion implantation for nano-FET

A method for fabricating a semiconductor device includes forming a fin extending along a first direction on a semiconductor substrate and forming a sacrificial gate electrode structure extending along a second direction substantially perpendicular to the first direction over the fin. The sacrificial gate electrode structure comprises a sacrificial gate dielectric layer and a sacrificial gate electrode layer disposed over the sacrificial gate dielectric layer. Opposing gate sidewall spacers are formed extending along the second direction, on opposing sides of the sacrificial gate electrode layer. The sacrificial gate electrode layer is removed to form a gate space. Fluorine is implanted into the gate sidewall spacers after removing the gate electrode layer by performing a first fluorine implantation. The sacrificial gate dielectric layer is removed and a high-k gate dielectric layer is formed in the gate space. Fluorine is implanted into the gate sidewall spacers and the fin after forming the high-k gate dielectric layer by performing a second fluorine implantation.

Method for fabricating a semiconductor device

In a method for manufacturing a semiconductor device, fin structures each having an upper portion and a lower portion, are formed. The lower portion is embedded in an isolation insulating layer disposed over a substrate and the upper portion protrudes the isolation insulating layer. A gate dielectric layer is formed over the upper portion of each of the fin structures. A conductive layer is formed over the gate dielectric layer. A cap layer is formed over the conductive layer. An ion implantation operation is performed on the fin structures with the cap layer. The ion implantation operation is performed multiple times using different implantation angles to introduce ions into one side surface of each of the fin structures.

Method of manufacturing semiconductor devices

A FinFET is provided including a channel region containing a constituent element and excess atoms, the constituent element belonging to a group of the periodic table of elements, wherein said excess atoms are nitrogen, or belong to said group of the periodic table of elements, and a concentration of said excess atoms in the channel region is in the range between about 10cmand about 10cm.

A semiconductor device, and a method of manufacturing, is provided. A dummy gate is formed on a semiconductor substrate. An interlayer dielectric (ILD) is formed over the semiconductor fin. A dopant is implanted into the ILD. The dummy gate is removed and an anneal is performed on the ILD. The implantation and the anneal lead to an enhancement of channel resistance by a reduction in interlayer dielectric thickness and to an enlargement of critical dimensions of a metal gate.

Implantation and annealing for semiconductor device

Growing community of inventors

Hsinchu, Taiwan

Chun-Feng Nieh