Nan Ya Technology Corporation

Chun-Cheng Liao

Yuan-Hsun Wu

The present application discloses a semiconductor device. The semiconductor device includes a first chip including a first substrate, a first redistribution layer above the first substrate, a first lower bonding pad positioned on the first redistribution layer, and a second lower bonding pad above the first substrate; and a second chip including a dense region and a loose region adjacent to the dense region, upper pads on the first lower bonding pad and the second lower bonding pad, second redistribution layers on the upper pads, and a first redistribution plug and a second redistribution plug respectively and correspondingly on the second redistribution layers. The first redistribution plug is at the dense region and includes a first aspect ratio. The second redistribution plug is at the loose region and includes a second aspect ratio less than the first aspect ratio.

Semiconductor device with redistribution plugs

A semiconductor device structure includes a first dielectric layer disposed over a semiconductor substrate, and a second dielectric layer disposed over the first dielectric layer. The semiconductor device structure also includes a first conductive plug disposed in the first dielectric layer, and a second conductive plug disposed in the second dielectric layer and directly over the first conductive plug. The semiconductor device structure further includes a silicide portion disposed between the first conductive plug and the second conductive plug.

Semiconductor device structure with silicide portion between conductive plugs

The present application discloses a method for fabricating a semiconductor device. The method includes providing a first chip comprising a first substrate, a first redistribution layer positioned above the first substrate, a first lower bonding pad positioned on the first redistribution layer, and a second lower bonding pad positioned above the first substrate and distant from the first lower bonding pad. The method also includes providing a second chip comprising a dense region and a loose region adjacent to the dense region; a plurality of upper pads positioned on the first lower bonding pad and the second lower bonding pad; and a plurality of second redistribution layers positioned on the plurality of upper pads. The method further performs bonding the second chip onto the first chip in a face-to-face manner, wherein the plurality of upper pads contact the first lower bonding pad and the second lower bonding pad.

Method for fabricating semiconductor device with redistribution plugs

A method for preparing a semiconductor device structure includes forming a first dielectric layer over a semiconductor substrate; forming a first conductive plug in the first dielectric layer; forming a polysilicon layer covering the first dielectric layer and the first conductive plug; transforming a portion of the polysilicon layer into a silicide portion; forming a second conductive plug directly over the silicide portion; and forming a second dielectric layer surrounding the second conductive plug.

Method for preparing semiconductor device structure with silicide portion between conductive plugs

The present disclosure relates to method for preparing a semiconductor device with a composite landing pad. The method includes forming a first dielectric layer over a semiconductor substrate. The semiconductor device also includes forming a lower metal plug and a barrier layer in the first dielectric layer. The lower metal plug is surrounded by the barrier layer. The semiconductor device further includes forming an inner silicide portion over the lower metal plug, and an outer silicide portion over the barrier layer. A topmost surface of the outer silicide portion is higher than a topmost surface of the inner silicide portion.

Method for preparing semiconductor device with composite landing pad

The present disclosure provides a method for preparing a semiconductor memory device with air gaps between conductive features. The method includes forming an isolation layer defining a first active region in a substrate; forming a first doped region in the first active region; forming a first word line buried in a first trench adjacent to the first doped region; and forming a high-level bit line contact positioned on the first doped region; forming a first air gap surrounding the high-level bit line contact. The forming of the first word line comprises: forming a lower electrode structure and an upper electrode structure on the lower electrode structure. The forming of the upper electrode structure comprises: forming a source layer substantially covering a sidewall of the first trench; forming a conductive layer on the source layer; and forming a work-function adjustment layer disposed between the source layer and the conductive layer.

Method for preparing semiconductor memory device with air gaps between conductive features

The present disclosure relates to a semiconductor device with a composite landing pad. The semiconductor device includes a first dielectric layer disposed over a semiconductor substrate. The semiconductor device also includes a lower metal plug and a barrier layer disposed in the first dielectric layer. The lower metal plug is surrounded by the barrier layer. The semiconductor device further includes an inner silicide portion disposed over the lower metal plug, and an outer silicide portion disposed over the barrier layer. A topmost surface of the outer silicide portion is higher than a topmost surface of the inner silicide portion.

Semiconductor device with composite landing pad for metal plug

The present disclosure provides a semiconductor memory device with air gaps between conductive features for reducing capacitive coupling and a method for preparing the semiconductor memory device. The semiconductor memory device includes an isolation layer defining a first active region in a substrate; a first doped region positioned in the first active region; a first word line buried in a first trench adjacent to the first doped region; a high-level bit line contact positioned on the first doped region; a first air gap surrounding the high-level bit line contact; wherein the first word line comprises a lower electrode structure and an upper electrode structure on the lower electrode structure; wherein the upper electrode structure comprises: a source layer substantially covering a sidewall of the first trench; a conductive layer on the source layer; and a work-function adjustment layer disposed between the source layer and the conductive layer.

Semiconductor memory device with air gaps between conductive features and method for preparing the same

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a plurality of plugs positioned above the substrate, a plurality of air gaps positioned adjacent to the plurality of plugs, and a plurality of capacitor structures positioned above the substrate.

Semiconductor device with air gaps and method for fabricating the same

The present application discloses a method for preparing a semiconductor device structure. The method includes: forming a ring structure over a substrate; performing an etching process to form an annular semiconductor fin under the ring structure; forming a processed area on a top portion of the substrate exposed by the annular semiconductor fin; selectively forming a spacer on a side surface of the annular semiconductor fin; forming a lower source/drain region on the surface of the substrate in contact with a bottom portion of the annular semiconductor fin; forming an inner gate structure in contact with an inner sidewall of the annular semiconductor fin and forming an outer gate structure in contact with an outer sidewall of the annular semiconductor fin; and forming an upper source/drain region on an upper portion of the annular semiconductor fin.

Method for preparing a semiconductor device structure with an annular semiconductor fin

A photolithography method for reducing effects of lens aberration. A photolithography apparatus is provided with a first reticle therein, having at least one first rectangular pattern thereon, a first photolithography is performed on a wafer by the photolithography apparatus to transfer the first rectangular pattern thereonto by simultaneously moving the first reticle and the wafer in a direction parallel to the short sides of the first rectangular pattern. The first reticle is replaced with a second reticle having at least one second rectangular pattern thereon and a second photolithography is performed by the photolithography apparatus to transfer the second rectangular pattern onto the wafer by simultaneously moving the second reticle and the wafer in a 90&#xb0; plus or minus rotation in a direction parallel to the short sides of the second rectangular pattern.

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Taipei, Taiwan

Chun-Cheng Liao