Micron Technology Incorporated

Round Rock Research, LLC

Chun Chen

Andrei Mihnea

Kirk D Prall

Paul J Rudeck

Graham Richard Wolstenholme

Guy T Blalock

Andrew Bicksler

Jeffrey Alan Kessenich

A method is provided for programming a memory cell. The memory cell is fabricated on a substrate and comprises a source region, a drain region, a floating gate, and a control gate. The memory cell has a threshold voltage selectively configurable into one of at least three programming states. The method includes generating a drain current between the drain region and the source region by applying a drain-to-source bias voltage between the drain region and the source region. The method further includes injecting hot electrons from the drain current to the floating gate by applying a gate voltage to the control gate. A selected threshold voltage for the memory cell corresponding to a selected one of the programming states is generated by applying a different selected gate voltage.

Programming methods for multi-level memory devices

The present invention provides a method and apparatus for forming a double-doped polysilicon floating gate in a semiconductor memory element. The method includes forming a first dielectric layer on a semiconductor substrate and forming a floating gate above the first dielectric layer, the floating gate comprised of a first layer doped with a first type of dopant material and a second layer doped with a second type of dopant material that is opposite the first type of dopant material in the first layer. The method further includes forming a second dielectric layer above the floating gate, forming a control gate above the second dielectric layer, and forming a source and a drain in the substrate.

Double-doped polysilicon floating gate

Floating-gate field-effect transistors or memory cells formed in isolated wells are useful in the fabrication of non-volatile memory arrays and devices. A column of such floating-gate memory cells are associated with a well containing the source/drain regions for each memory cell in the column. These wells are isolated from source/drain regions of other columns of the array. Fowler-Nordheim tunneling can be used to program and erase such floating-gate memory cells either on an individual basis or on a bulk or block basis.

Contactless uniform-tunneling separate p-well (CUSP) non-volatile memory array architecture, fabrication and operation

Methods and apparatus are described to facilitate forming memory devices with low resistance polysilicon local interconnects that allow a smaller array feature size and therefore facilitate forming arrays of a denser array format. Embodiments of the present invention are formed utilizing a wet etch process that has a high selectivity, allowing the deposition and etching of polysilicon local interconnects to source regions of array transistors. By providing for a local interconnect of polysilicon, a smaller source region and/or drain region can also be utilized, further decreasing the required word line spacing. Low resistance polysilicon local source interconnects can also couple to an increased number of memory cells, thereby reducing the number of contacts made to an array ground.

Method for forming a floating gate memory with polysilicon local interconnects

Method for forming an array with polysilicon local interconnects

A method for forming a flash memory device having a local interconnect connecting source regions of a plurality of transistors within a sector allows for a highly selective wet etch of a dielectric region overlying the source region. An embodiment of the method comprises the use of an etch-resistant layer covering various features such as any gate oxide remaining over the source region, spacers along sidewalls of the transistor stacks, and a capping layer of the transistor. An in-process semiconductor device resulting from the inventive method is also disclosed.

Method and apparatus for a flash memory device comprising a source local interconnect

Methods for neutralizing holes in tunnel oxides of floating-gate memory cells and devices using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a control gate voltage of a second polarity.

Methods for neutralizing holes in tunnel oxides of floating-gate memory cells and devices

Methods for erasing flash memory using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a control gate voltage of a second polarity during an erase period.

Methods for erasing flash memory

Methods for neutralizing holes in tunnel oxides in tunnel oxides of floating-gate memory cells and devices

Flash memory supporting methods for erasing memory cells using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a control gate voltage of a second polarity during an erase period.

Flash memory

An embodiment of a floating-gate memory cell has a tunnel dielectric layer formed overlying a semiconductor substrate; a drain region formed in a semiconductor substrate adjacent a first side of the tunnel dielectric layer, a source region formed in a semiconductor substrate adjacent a second side of the tunnel dielectric layer, a floating-gate layer formed overlying the tunnel dielectric layer, a control-gate layer formed overlying the floating-gate layer, and an intergate dielectric layer formed interposed between the floating-gate layer and the control gate layer. The control-gate layer includes a silicide layer in contact with an underlying polysilicon layer. There is no interposing dielectric layer between the control-gate layer and an overlying bulk insulator layer, and a width of the silicide layer is substantially equal to a width of the polysilicon layer.

Growing community of inventors

Boise, ID, United States of America

Chun Chen