Samsung Electronics Co., Ltd.

Chull-Soo Kim

Hyun-Soon Jang

Ho-cheol Lee

Yun-Ho Choi

Si-Yeol Lee

Tae-jin Kim

Churoo Park

Myung-Ho Kim

Seung-Hun Lee

Seung-hun Lee

A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU). The synchronous DRAM receives an external clock and includes a plurality of memory banks each including a plurality of memory cells and operable in either an active cycle or a precharge cycle, a circuit for receiving a row address strobe signal and latching a logic level of the row address strobe signal in response to the clock, an address input circuit for receiving an externally generated address selecting one of the memory banks, and a circuit for receiving the latched logic level and the address from the address input circuit and for outputting an activation signal to the memory bank selected by the address and an inactivation signals to unselected memory banks when the latched logic level is a first logic level, so that the selected memory bank responsive to the activation signal operates in the active cycle while the unselected memory banks responsive to the inactivation signals operate in the precharge cycle.

Multi-bank dynamic random access memory devices having all bank precharge capability

Circuit in a semiconductor memory for programming operation modes of the

Synchronous dram having a plurality of latency modes

System for selecting one of a plurality of memory banks for use in an

Semiconductor memory having a plurality of I/O buses

A data output buffer of a semiconductor memory device using a clock having a fixed period from outside. The data output buffer has a data input part controlled and synchronized with a clock, for inputting data; a data latch device for latching data output through the data input part to thereby set up a predetermined delay time; a control signal input part controlled by the clock, for inputting a control signal; a latch controller for latching the control signal output through the control signal input part during a given time; a data output driver for receiving an output signal from the data latch device, the data output driver being controlled by the output signal of the latch controller; and an output device connected to the data output driver, for providing the data.

Data output buffer of a semiconducter memory device

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Suwon, South Korea

Chull-Soo Kim