Megica Corporation

Taiwan Semiconductor Manufacturing Comp. Ltd.

Megic Corporation

Qualcomm Incorporated

Vanguard International Semiconductor Corporation

Chuen-Jye Lin

Ching-Cheng Huang

Ming-Ta Lei

Mou-Shiung Lin

Jin Yuan Lee

Jin-Yuan Lee

Pei-Haw Tsao

Ming Ta Lei

Chender Huang

Chao-Yuan Su

Tsung-Chieh Chen

Kuang-Ho Liao

Chen-Der Huang

The invention provides a new method and chip scale package is provided. The inventions starts with a substrate over which a contact point is provided, the contact point is exposed through an opening created in the layer of passivation and a layer of polymer or elastomer. A barrier/seed layer is deposited, a first photoresist mask is created exposing the barrier/seed layer where this layer overlies the contact pad and, contiguous therewith, over a surface area that is adjacent to the contact pad and emanating in one direction from the contact pad. The exposed surface of the barrier/seed layer is electroplated for the creation of interconnect traces. The first photoresist mask is removed from the surface of the barrier/seed layer. A second photoresist mask, defining the solder bump, is created exposing the surface area of the barrier/seed layer that is adjacent to the contact pad and emanating in one direction from the contact pad. The solder bump is created in accordance with the second photoresist mask, the second photoresist mask is removed from the surface of the barrier/seed layer, exposing the electroplating and the barrier/seed layer with the metal plating overlying the barrier/seed layer. The exposed barrier/seed layer is etched in accordance with the pattern formed by the electroplating, reflow of the solder bump is optionally performed.

Low fabrication cost, high performance, high reliability chip scale package

In accordance with the objectives of the invention a new method is provided for the creation of metal bumps over surfaces of I/O pads. Contact pads are provided over the surface of a layer of dielectric. The aluminum of the I/O pads, which have been used as I/O pads during wafer level semiconductor device testing, is completely or partially removed over a surface area that is smaller than the surface area of the contact pad using methods of metal dry etching or wet etching. The contact pad can be accessed either by interconnect metal created in a plane of the contact pad or by via that are provided through the layer of dielectric over which the contact pad has been deposited. The process can be further extended by the deposition, patterning and etching of a layer of polyimide over the layer of passivation that serves to protect the contact pad.

Reliable metal bumps on top of I/O pads after removal of test probe marks

A package structure and fabrication method thereof. The structure includes a substrate having a terminal, a chip overlying the substrate, the chip having an active surface, having a center region and periphery region, the periphery region having an electrode thereon, a patterned cover plate overlying the chip and exposing the electrode, a conductive material electrically connecting the electrode and terminal, and an encapsulant covering the terminal, conductive material, and electrode, but exposing the cover plate overlying the center region of the chip.

Fabrication method of package structure with simplified encapsulation structure and simplified wiring

A new method and package is provided for the mounting of semiconductor devices that have been provided with small-pitch Input/Output interconnect bumps. Fine pitch solder bumps, consisting of pillar metal and a solder bump, are applied directly to the I/O pads of the semiconductor device, the device is then flip-chip bonded to a substrate. Dummy bumps may be provided for cases where the I/O pads of the device are arranged such that additional mechanical support for the device is required.

Structure and manufacturing method of a chip scale package

Structure and manufacturing method of a chip scale package with low fabrication cost, fine pitch and high reliability solder bump

Package structure and fabrication method thereof

A substrate design to improve chip package reliability is provided. The chip package includes a substrate having a ceramic layer formed in a recess. A die is attached to the substrate on the ceramic layer. The substrate may be attached to a printed circuit board. The substrate may be fabricated by forming a recess in a substrate, such as a multi-layer substrate formed of organic dielectric materials. A ceramic layer is then affixed to the substrate in the recess. A die may be attached to the ceramic layer and the substrate may be attached to a printed circuit board.

Substrate design to improve chip package reliability

A new method and chip scale package is provided. A point of electrical contact over a substrate is exposed through an opening created through overlying layers of passivation and polymer or elastomer, deposited over the substrate. A barrier/seed layer is deposited. A first photoresist mask exposes the barrier/seed layer where this layer overlies and is adjacent to the contact pad. The exposed surface of the barrier/seed layer is electroplated. The first photoresist mask is removed, a second photoresist mask is created to define the solder bump exposing a surface area of the barrier/seed layer not overlying the contact pad. The solder bump is created, the second photoresist mask is removed. The exposed barrier/seed layer is etched in accordance with the electroplating, reflow of the solder bump is optionally performed.

Method of making a low fabrication cost, high performance, high reliability chip scale package

Growing community of inventors

Taichung, Taiwan

Chuen-Jye Lin