Taiwan Semiconductor Manufacturing Comp. Ltd.

Universal Scientific Industrial Co., Ltd.

University Scientific Industrial Co., Ltd.

Chuei-Tang Wang

Chen-Hua Douglas Yu

Chung-Hao Tsai

Chieh-Yen Chen

Jeng-Shien Hsieh

Wei-Ting Chen

Tzu-Chun Tang

Kai-Chiang Wu

Monsen Liu

Chih-Yuan Chang

Hao-Yi Tsai

Vincent Chen

En-Hsiang Yeh

Chih-Chieh Chang

Chun-Lin Lu

Che-Wei Hsu

Hung-Yi Kuo

Ming Hung Tseng

Hsing-Kuo Hsia

Wei Ling Chang

Lai Wei Chih

Shih-Ya Huang

Tin-Hao Kuo

Ching-Feng Yang

Shou-Zen Chang

Yen-Ping Wang

Chung-Shi Liu

Han-Ping Pu

Shou Zen Chang

Hao-Hsiang Chuang

Ching-Hua Hsieh

Chao-Wen Shih

Yen-Liang Lin

Wei-Ting Lin

Ming-Kai Liu

Chih-Lin Chen

Yu-Kuang Liao

Wei-Heng Lin

Shih-Wei Liang

Albert Wan

Shih-Chang Ku

In-Tsang Lin

Der-Chyang Yeh

Kuo-Chung Yee

Alan S Roth

Eric Soenen

Pei-Hsuan Lee

Chien-Ling Hwang

Ying-Chih Hsu

Chien-Yuan Huang

Yu-Ting Chiu

Jui-Chang Kuo

Chia-Chia Lin

Jeng-Shieh Hsieh

Chun-Wen Lin

Hsien-Wei Chen

Chewn-Pu Jou

Yih Wang

Hsiu-Jen Lin

Kuo-Ji Chen

Fong-yuan Chang

Yu-Chih Huang

Jiun-Yi Wu

Chih-Hsuan Tai

Chi-Hui Lai

Ching-Fang Chen

Chien-Hsun Chen

Ying-Cheng Tseng

Chia-Lun Chang

Ting-Ting Kuo

Ban-Li Wu

Shao-Yu Li

Chiahung Liu

Chang-Fen Hu

Chih-Peng Lin

Huan-Neng Chen

Stefan Rusu

Fu-Lung Hsueh

Feng Wei Kuo

Wen-Shiang Liao

Tung-Liang Shao

Sen-Kuei Hsu

Weiwei Song

Kuo-Hsien Liao

Min-Chien Hsiao

Rabiul Islam

Wei-Chih Lai

Kuan-Hsing Li

Kuo-Hua Tseng

Yeh En-Hsiang

Jia-Yang Chen

Hui-Chung Lee

Yu-Sheng Huang

In an embodiment, a device includes: a processor die including circuit blocks, the circuit blocks including active devices of a first technology node; a power gating die including power semiconductor devices of a second technology node, the second technology node larger than the first technology node; and a first redistribution structure including first metallization patterns, the first metallization patterns including power supply source lines and power supply ground lines, where a first subset of the circuit blocks is electrically coupled to the power supply source lines and the power supply ground lines through the power semiconductor devices, and a second subset of the circuit blocks is permanently electrically coupled to the power supply source lines and the power supply ground lines.

Integrated circuit package and method

An integrated circuit structure includes a metal pad, a passivation layer including a portion over the metal pad, a first polymer layer over the passivation layer, and a first Post-Passivation Interconnect (PPI) extending into to the first polymer layer. The first PPI is electrically connected to the metal pad. A dummy metal pad is located in the first polymer layer. A second polymer layer is overlying the first polymer layer, the dummy metal pad, and the first PPI. An Under-Bump-Metallurgy (UBM) extends into the second polymer layer to electrically couple to the dummy metal pad.

Polymer layers embedded with metal pads for heat dissipation

A package assembly and a manufacturing method thereof are provided. The package assembly includes a first package component and an optical signal port disposed aside the first package component. The first package component includes a first die including an electronic integrated circuit, a first insulating encapsulation laterally covering the first die, a redistribution structure disposed on the first die and the first insulating encapsulation, and a second die including a photonic integrated circuit and electrically coupled to the first die through the redistribution structure. The optical signal port is optically coupled to an edge facet of the second die of the first package component.

Package assembly and manufacturing method thereof

A package structure includes at least one integrated circuit component, an insulating encapsulation, and a redistribution structure. The at least one integrated circuit component includes a semiconductor substrate, an interconnection structure disposed on the semiconductor substrate, and signal terminals and power terminals located on and electrically connecting to the interconnection structure. The interconnection structure is located between the semiconductor substrate and the signal terminals and between the semiconductor substrate and the power terminals, and where a size of the signal terminals is less than a size of the power terminals. The insulating encapsulation encapsulates the at least one integrated circuit component. The redistribution structure is located on the insulating encapsulation and electrically connected to the at least one integrated circuit component.

Package structure

An integrated fan-out (InFO) package includes a die, an encapsulant, and a horn antenna. The die has an active surface and a rear surface opposite to the active surface. The encapsulant laterally encapsulates the die. The horn antenna is electrically connected to the die. The horn antenna includes a top wall and a bottom wall respectively located on two opposite sides of the die and the encapsulant. A portion of the top wall is located within a span of the active surface of the die. A portion of the bottom wall is located within a span of the rear surface of the die.

Integrated fan-out package

A method includes forming a reconstructed wafer, which includes forming a redistribution structure over a carrier, bonding a first plurality of memory dies over the redistribution structure, bonding a plurality of bridge dies over the redistribution structure, and bonding a plurality of logic dies over the first plurality of memory dies and the plurality of bridge dies. Each of the plurality of bridge dies interconnects, and is overlapped by corner regions of, four of the plurality of logic dies. A second plurality of memory dies are bonded over the plurality of logic dies. The plurality of logic dies form a first array, and the second plurality of memory dies form a second array.

Architecture for computing system package

A chip package includes a redistribution layer, at least one first semiconductor chip, an integrated fan-out package, and an insulating encapsulation. The at least one first semiconductor chip and the integrated fan-out package are electrically connected to the redistribution layer, wherein the at least one first semiconductor chip and the integrated fan-out package are located on a surface of the redistribution layer and electrically communicated to each other through the redistribution layer, and wherein the integrated fan-out package includes at least one second semiconductor chip. The insulating encapsulation encapsulates the at least one first semiconductor chip and the integrated fan-out package.

Chip package and manufacturing method thereof

A package structure includes a conductive feature structure, a die, an adhesive layer, an insulator, a through via, and an encapsulant. The die is disposed over the conductive feature structure. The adhesive layer is disposed below the die. The insulator is disposed between the adhesive layer and a polymer layer of the conductive feature structure. The through via extends through the insulator to connect to the conductive feature structure. The encapsulant is disposed on the insulator and the conductive feature structure, laterally encapsulating the die and the through via, and between the through via and the insulator. The insulator has a coefficient of thermal expansion less than a coefficient of thermal expansion of the encapsulant.

Package structure and method of manufacturing the same

In an embodiment, a structure includes: a processor device including logic devices; a first memory device directly face-to-face bonded to the processor device by metal-to-metal bonds and by dielectric-to-dielectric bonds; a first dielectric layer laterally surrounding the first memory device; a redistribution structure over the first dielectric layer and the first memory device, the redistribution structure including metallization patterns; and first conductive vias extending through the first dielectric layer, the first conductive vias connecting the metallization patterns of the redistribution structure to the processor device.

A device includes a first semiconductor device including a first bonding layer; a second semiconductor device bonded to the first bonding layer of the first semiconductor device; thermal structures disposed beside the second semiconductor device and on the first bonding layer, wherein the thermal structures include a conductive material, wherein the thermal structures are electrically isolated from the first semiconductor device and from the second semiconductor device; an encapsulant disposed on the first bonding layer, wherein the encapsulant surrounds the second semiconductor device and surrounds the thermal structures; and a second bonding layer disposed over the encapsulant, the thermal structures, and the second semiconductor device.

Semiconductor package and method

In an embodiment, a device includes: a first die array including first integrated circuit dies, orientations of the first integrated circuit dies alternating along rows and columns of the first die array; a first dielectric layer surrounding the first integrated circuit dies, surfaces of the first dielectric layer and the first integrated circuit dies being planar; a second die array including second integrated circuit dies on the first dielectric layer and the first integrated circuit dies, orientations of the second integrated circuit dies alternating along rows and columns of the second die array, front sides of the second integrated circuit dies being bonded to front sides of the first integrated circuit dies by metal-to-metal bonds and by dielectric-to-dielectric bonds; and a second dielectric layer surrounding the second integrated circuit dies, surfaces of the second dielectric layer and the second integrated circuit dies being planar.

Packaged semiconductor devices including heat-dissipating structures and methods of forming the same are disclosed. In an embodiment, a semiconductor package includes a semiconductor die including a substrate, a front-side interconnect structure on a front-side of the substrate, and a backside interconnect structure on a backside of the substrate opposite the front-side interconnect structure; a support die disposed on the front-side interconnect structure; a heat-dissipating structure on the support die, the heat-dissipating structure being thermally coupled to the semiconductor die and the support die; a redistribution structure on the backside interconnect structure opposite the substrate, the redistribution structure being electrically coupled to the semiconductor die; and an encapsulant on the redistribution structure and adjacent to side surfaces of the semiconductor die, the support die, and the heat-dissipating structure.

Heat-dissipating structures for semiconductor devices and methods of manufacture

A circuit structure is provided. The circuit structure may include a first die area including an output gate, a second die area including a circuit and an input gate and a die-to-die interconnect. The input gate may include a transistor. The circuit may be connected between the die-to-die interconnect and a gate region of the transistor. The circuit may include a MOS transistor. A first source/drain region of the MOS transistor may be connected to the die-to-die interconnect.

Semiconductor and circuit structures, and related methods

A semiconductor package includes electric integrated circuit dies, photoelectric integrated circuit dies, and an inter-chip waveguide. The electric integrated circuit dies are laterally encapsulated by a first insulating encapsulant. The photoelectric integrated circuit dies are laterally encapsulated by a second insulating encapsulant. Each one of photoelectric integrated circuit dies includes an optical input/output terminal. The inter-chip waveguide is disposed over the second insulating encapsulant, wherein the photoelectric integrated circuit dies are optically communicated with each other through the inter-chip waveguide.

Semiconductor package and method of forming the same

Systems, devices and methods of manufacturing a system on silicon wafer (SoSW) device and package are described herein. A plurality of functional dies is formed in a silicon wafer. Different sets of masks are used to form different types of the functional dies in the silicon wafer. A first redistribution structure is formed over the silicon wafer and provides local interconnects between adjacent dies of the same type and/or of different types. A second redistribution structure may be formed over the first redistribution layer and provides semi-global and/or global interconnects between non-adjacent dies of the same type and/or of different types. An optional backside redistribution structure may be formed over a second side of the silicon wafer opposite the first redistribution layer. The optional backside redistribution structure may provide backside interconnects between functional dies of different types.

System, device and methods of manufacture

Growing community of inventors

Taichung, Taiwan

Chuei-Tang Wang