Taiwan Semiconductor Manufacturing Comp. Ltd.

Chuang Chihchous

Yu-Lung Yeh

Yung-Hsiang Chen

Yen-Hsiu Chen

Wei-Liang Chen

Hung-San Lu

Ting-Ying Wu

Cheng-Hsien Chen

A plating membrane includes a support structure extending radially outward from a nozzle that is to direct a flow of a plating solution toward a wafer. The plating membrane also includes a frame, supported by the support structure, having an inner wall that is angled outward from the nozzle. The outward angle of the inner wall relative to the nozzle directs a flow of plating solution from the nozzle in a manner that increases uniformity of the flow of the plating solution toward the wafer, reduces the amount of plating solution that is redirected inward toward the center of the plating membrane, reduces plating material voids in trenches of the wafer (e.g., high aspect ratio trenches), and/or the like.

Plating membrane

A semiconductor arrangement includes an isolation structure having a first electrical insulator layer in a trench in a semiconductor substrate and a second electrical insulator layer in the trench and over the first electrical insulator layer.

Semiconductor arrangement comprising isolation structure comprising at least two electrical insulator layers

Semiconductor arrangement including a first electrical insulator layer and a second electrical insulator layer and method of making

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Fongshan, Taiwan

Chuang Chihchous