International Rectifier Corporation

Infineon Technologies Americas Corp.

International Business Machines Corporation

Infineon Technologies Ag

Infineon Technologies Austria Ag

Chuan Cheah

Eung San Cho

Kunzhong Hu

Andrew Neil Sawle

Michael A Briere

Daniel Marvin Kinzer

Dae Keun Park

Christopher Davis

Bharat Shivkumar

Danny Clavette

Timothy Alan Phillips

Naresh Thapar

Jorge Munoz

EungSan Cho

Srini Thiruvenkatachari

Josef Hoeglauer

Christopher P Schaffer

Bo Yang

Tobias Polster

Dan Kinzer

Roberto Martinez

Jorge Munos

Jobelito Anjao Guanzon

Kevin Hu

A method of processing a semiconductor wafer includes: forming an electronic device at each die location of the semiconductor wafer; partially forming a frontside metallization over a frontside of the semiconductor wafer at each die location; partially forming a backside metallization over a backside of the semiconductor wafer at each die location; and after partially forming both the frontside metallization and the backside metallization but without completing either the frontside metallization or the backside metallization, singulating the semiconductor wafer between the die locations to form a plurality of individual semiconductor dies, wherein the partially formed frontside metallization and the partially formed backside metallization have a same composition. Semiconductor dies and methods of producing semiconductor modules are also described.

Method of processing a semiconductor wafer, semiconductor die, and method of producing a semiconductor module

A semiconductor device package includes a die pad having a die attach surface, a first lead that is spaced apart and extends away from a first side of the die pad, and a semiconductor die mounted on the die attach surface. The semiconductor die includes a first bond pad disposed on an upper side of the semiconductor die that is opposite the die attach surface. A first clip electrically connects the first lead to the first bond pad. The first bond pad is elongated with first and second longer edge sides that are opposite one another and extend along a length of the first bond pad. The semiconductor die is oriented such that the first and second longer edge sides of the first bond pad are non-parallel to a first current flow direction of the first clip that extends between the first bond pad and the first lead.

Bond pad and clip configuration for packaged semiconductor device

In some examples, a device includes a substrate and a conductive pad extending through the substrate, wherein the substrate is coupled to the conductive pad at an interface and the substrate extends laterally from the interface to define a substrate extension. In some examples, the device also includes a semiconductor die mounted on the first side of the substrate. In some examples, the device includes a breakpoint that defines a torque tolerance that is less than a torque tolerance of the device at other points. In some examples, the device is configured to break at the breakpoint in response to force being applied to the substrate extension on the first side of the substrate.

Breakable substrate for semiconductor die

There are disclosed herein various implementations of a compact high-voltage semiconductor package. In one exemplary implementation, such a semiconductor package includes a power transistor, as well as a drain contact, a source contact, and a gate contact to provide external connections to the power transistor. The semiconductor package also includes a contour element formed between the drain contact and the source contact in the semiconductor package. The contour element increases a creepage distance between the drain contact and the source contact in the semiconductor package so as to increase a breakdown voltage of the semiconductor package.

Compact high-voltage semiconductor package

According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to an output terminal, and a control gate for being driven by a driver IC. The stacked half-bridge package also includes a sync transistor having a sync drain for connection to the output terminal, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver IC. A current carrying layer is situated on the sync drain; the control transistor and the sync transistor being stacked on one another, where the current carrying layer provides a high current connection between the sync drain and the control source.

Stacked half-bridge package

According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to an output terminal, and a control gate for being driven by a driver IC. The stacked half-bridge package further includes a sync transistor having a sync drain for connection to the output terminal, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver IC. The control and sync transistors are stacked on opposite sides of a common conductive leadframe with the common conductive leadframe electrically and mechanically coupling the control source with the sync drain. The common conductive leadframe thereby serves as the output terminal.

One exemplary disclosed embodiment comprises a high power semiconductor package configured as a buck converter having a control transistor and a sync transistor disposed on a common leadframe pad, a driver integrated circuit (IC) for driving the control and sync transistors, and conductive clips electrically coupling the top surfaces of the transistors to substrate pads such as leadframe pads. In this manner, the leadframe and the conductive clips provide efficient grounding or current conduction by direct mechanical connection and large surface area conduction, thereby enabling a package with significantly reduced electrical resistance, form factor, complexity, and cost when compared to conventional packaging methods using wirebonds for transistor interconnections.

Semiconductor package with conductive clips

According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to a common conductive clip, and a control gate for being driven by a driver IC. The stacked half-bridge package also includes a sync transistor having a sync drain for connection to the common conductive clip, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver IC. The control and sync transistors are stacked on opposite sides of the common conductive clip with the common conductive clip electrically and mechanically coupling the control source with the sync drain, where the common conductive clip has a conductive leg for providing electrical and mechanical connection to an output terminal leadframe.

Power semiconductor package with a common conductive clip

A semiconductor package that includes a semiconductor die and a heat spreader thermally coupled to the semiconductor and disposed at least partially within the molded housing of the package.

Semiconductor package with heat spreader

Stacked half-bridge package with a common leadframe

Some exemplary embodiments of a III-nitride power device including a HEMT with multiple interconnect metal layers and a solderable front metal structure using solder bars for external circuit connections have been disclosed. The solderable front metal structure may comprise a tri-metal such as TiNiAg, and may be configured to expose source and drain contacts of the HEMT as alternating elongated digits or bars. Additionally, a single package may integrate multiple such HEMTs wherein the front metal structures expose alternating interdigitated source and drain contacts, which may be advantageous for DC-DC power conversion circuit designs using III-nitride devices. By using solder bars for external circuit connections, lateral conduction is enabled, thereby advantageously reducing device Rdson.

III-Nitride device with solderable front metal

Some exemplary embodiments of high voltage cascoded III-nitride semiconductor package utilizing clips on a package support surface have been disclosed. One exemplary embodiment comprises a III-nitride transistor attached to a package support surface and having an anode of a diode stacked over a source of the III-nitride transistor, a first conductive clip coupled to a gate of the III-nitride transistor and the anode of the diode, and a second conductive clip coupled to a drain of the III-nitride transistor. The conductive clips are connected to the package support surface and expose respective flat portions that are surface mountable. In this manner, reduced package footprint, improved surge current capability, and higher performance may be achieved compared to conventional wire bonded packages. Furthermore, since a low cost printed circuit board (PCB) may be utilized for the package support surface, expensive leadless fabrication processes may be avoided for cost effective manufacturing.

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Torrance, CA, United States of America

Chuan Cheah