Taiwan Semiconductor Manufacturing Comp. Ltd.

Chu-Yun Fu

Syun-Ming Jang Jang

Chen-Hua Douglas Yu

Chen-Nan Yeh

Shu-Tine Yang

Ding-Yuan Chen

Hung-Ming Chen

Hung-Ta Lin

Shin-Yeh Huang

Chia-Shiung Tsai

Tze-Liang Lee

Jhon-Jhy Liaw

Hun-Jan Tao

Pei-Ren Jeng

Ying-Ho Chen

Chih-Tang Peng

Chyi Shyuan Chern

Cheng-Hung Chang

Hao-Ming Lien

Chih-Cheng Lu

Jui-Hei Huang

Yihang Chiu

Shau-Lin Shue

Jin-Yuan Lee

Kong-Beng Thei

Mei-Yun Wang

Chih-Wei Chang

Huan-Just Lin

Chii-Ming M Wu

Weng Chang

Liang-Gi Yao

Hung-Chang Hsieh

Cheng-Tung Lin

Chung-Long Chang

Ming-Huan Tsai

Yi-Ming Sheu

Jyh-Cherng Sheu

Kuo-Chyuan Tzeng

Yuan-Hung Chiu

Yu-Rung Hsu

Fang-Cheng Chen

Ju-Wang Hsu

Li-Chih Chao

Shwangming Jeng

Tung-Ching Tseng

Chi-Hsun Hsieh

Chuan-Ping Hou

Kuei-Ying Lee

Ying-Ying Wang

So-Wein Kuo

Ruey-Lian Hwang

Li-Jen Chen

Yao-Hsiang Chen

Yu-Rang Hsu

Chuang-Ping Hou

Chang Wen

Jang Syun Ming

Chin-Hwa Hsieh

Yuan-Hunh Chiu

Syung-Ming Jang

A semiconductor device including reentrant isolation structures and a method for making such a device. A preferred embodiment comprises a substrate of semiconductor material forming at least one isolation structure having a reentrant profile and isolating one or more adjacent operational components. The reentrant profile of the at least one isolation structure is formed of substrate material and is created by ion implantation, preferably using oxygen ions applied at a number of different angles and energy levels. In another embodiment the present invention is a method of forming an isolation structure for a semiconductor device performing at least one oxygen ion implantation.

Method of fabricating semiconductor device isolation structure

A fin field effect transistor (FinFET) including a first insulation region and a second insulation region and fin there between. A gate stack is disposed over a first portion of the fin. A strained source/drain material is disposed over a second portion of the fin. The strained source/drain material has a flat top surface extending over the first and second insulation regions. The first insulation region may include a tapered top surface.

Fin field effect transistor

A method of fabricating a fin field effect transistor (FinFET) including forming a first insulation region and a second insulation region and fin there between. The method further includes forming a gate stack over a portion of the fin and over a portion of the first and second insulation regions. The method further includes tapering the top surfaces of the first and second insulation regions not covered by the gate stack.

A fin field effect transistor including a first insulation region and a second insulation region over a top surface of a substrate. The first insulation region includes tapered top surfaces, and the second insulation region includes tapered top surfaces. The fin field effect transistor further includes a fin extending above the top surface between the first insulation region and the second insulation region. The fin includes a first portion having a top surface below the tapered top surfaces of the first insulation region. The fin includes a second portion having a top surface above the tapered top surfaces of the first insulation region.

The present disclosure provides a method of fabricating a FinFET element including providing a substrate including a first fin and a second fin. A first layer is formed on the first fin. The first layer comprises a dopant of a first type. A dopant of a second type is provided to the second fin. High temperature processing of the substrate is performed on the substrate including the formed first layer and the dopant of the second type.

Method of fabrication of a FinFET element

A method of forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric over the semiconductor substrate, wherein the semiconductor substrate and a sidewall of the gate dielectric has a joint point; forming a gate electrode over the gate dielectric; forming a mask layer over the semiconductor substrate and the gate electrode, wherein a first portion of the mask layer adjacent the joint point is at least thinner than a second portion of the mask layer away from the joint point; after the step of forming the mask layer, performing a halo/pocket implantation to introduce a halo/pocket impurity into the semiconductor substrate; and removing the mask layer after the halo/pocket implantation.

Self-aligned halo/pocket implantation for reducing leakage and source/drain resistance in MOS devices

A FinFET is described, the FinFET includes a substrate including a top surface and a first insulation region and a second insulation region over the substrate top surface comprising tapered top surfaces. The FinFET further includes a fin of the substrate extending above the substrate top surface between the first and second insulation regions, wherein the fin includes a recessed portion having a top surface lower than the tapered top surfaces of the first and second insulation regions, wherein the fin includes a non-recessed portion having a top surface higher than the tapered top surfaces. The FinFET further includes a gate stack over the non-recessed portion of the fin.

Fin held effect transistor

A method of fabricating an isolation structure including forming a trench in a top surface of a substrate and partially filling the trench with a first oxide, wherein the first oxide is a pure oxide. Partially filling the trench includes forming a liner layer in the trench and forming the first oxide over the liner layer using silane and oxygen precursors at a pressure less than 10 milliTorr (mTorr) and a temperature ranging from about 500&#xb0; C. to about 1000&#xb0; C. The method further includes producing a solid reaction product in a top portion of the first oxide. The method further includes sublimating the solid reaction product by heating the substrate in a chamber at a temperature from 100&#xb0; C. to 200&#xb0; C. and removing the sublimated solid reaction product by flowing a carrier gas over the substrate. The method further includes filling the trench with a second oxide.

Method for fabricating an isolation structure

The disclosure relates to a fin field effect transistor (FinFET). An exemplary structure for a FinFET comprises a substrate comprising a top surface; a first insulation region and a second insulation region over the substrate top surface comprising tapered top surfaces; a fin of the substrate extending above the substrate top surface between the first and second insulation regions, wherein the fin comprises a recessed portion having a top surface lower than the tapered top surfaces of the first and second insulation regions, wherein the fin comprises a non-recessed portion having a top surface higher than the tapered top surfaces; and a gate stack over the non-recessed portion of the fin.

FinFET and method of fabricating the same

The invention relates to integrated circuit fabrication, and more particularly to an electronic device with an isolation structure made having almost no void. An exemplary method for fabricating an isolation structure, comprising: providing a substrate; forming a trench in the substrate; partially filling the trench with a first silicon oxide; exposing a surface of the first silicon oxide to a vapor mixture comprising NH3 and a fluorine-containing compound; heating the substrate to a temperature between 100&#xb0; C. to 200&#xb0; C.; and filling the trench with a second silicon oxide, whereby the isolation structure made has almost no void.

A method of forming an integrated circuit device includes providing a semiconductor substrate; forming a gate structure on the semiconductor substrate; and performing a pre-amorphized implantation (PAI) by implanting a first element selected from a group consisting essentially of indium and antimony to a top portion of the semiconductor substrate adjacent to the gate structure. The method further includes, after the step of performing the PAI, implanting a second element different from the first element into the top portion of the semiconductor substrate. The second element includes a p-type element when the first element includes indium, and includes an n-type element when the first element includes antimony.

Fabrication of source/drain extensions with ultra-shallow junctions

A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric layer on the semiconductor substrate; forming a first silicon-containing layer on the gate dielectric layer, wherein the first silicon-containing layer is substantially free from p-type and n-type impurities; forming a second silicon-containing layer over the first silicon-containing layer, wherein the second silicon-containing layer comprises an impurity; and performing an annealing to diffuse the impurity in the second silicon-containing layer into the first silicon-containing layer.

Polysilicon gate formation by in-situ doping

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Hsinchu, Taiwan

Chu-Yun Fu