International Business Machines Corporation

Samsung Electronics Co., Ltd.

Globalfoundries Inc.

Chartered Semiconductor Manufacturing Ltd (corporation)

Freescale Semiconductor,inc.

The State University of New York

Christopher V Baiocco

Xiangdong Chen

Daniel J Jaeger

Young Way Teh

Deleep R Nair

Helen Wang

Carl John Radens

Michael Patrick Chudzik

Jay M Shah

Young Gun Ko

Wenzhi Gao

Effendi Leobandung

Dureseti Chidambarrao

Kevin K Chan

Ying Di Zhang

Fei Liu

Douglas Duane Coolbaugh

Min Yang

Dae-Gyu Park

Xinhui Wang

Voon-Yew Thean

Masaharu Kobayashi

Da Zhang

Jae-Eun Park

Michael Vincent Aquilino

An L Steegen

Young-Hee Kim

Atul Champaklal Ajmera

Daewon Yang

Jin Zheng Wallner

Melanie J Sherony

Gerald L Leake

Weipeng Li

Laura S Chadwick

Junjung Kim

Haraprasad Nanjundappa

Basanth Jagannathan

Jie Chen

A semiconductor structure can include an active device FET region having a FET and a photonics region having a photonic device including a waveguide. A semiconductor structure can include an active device FET region having a FET and a trench isolation region having a photonic device that includes a waveguide. A method can include forming a FET at an active device FET region of a semiconductor structure. A method can include forming a photonic device at a trench isolation region of a semiconductor structure.

Method and structure for integrating photonics with CMOs

Various embodiments include approaches for analyzing integrated circuit (IC) designs. In some cases, an approach includes: defining extraction parameters for the design of the IC for each of a set of failure modes; testing the design of the IC for a failure mode in the set of failure modes; identifying a defined extraction parameter from the design of the IC for at least one of the set of failure modes; correlating the identified defined extracted parameter and each of the at least one failure mode for the design of the IC; and creating a normalized parameter equation representing the correlation of the identified defined extraction parameter with the at least one failure mode for the design of the IC in numerical form.

Integrated circuit (IC) design analysis and feature extraction

Oxygen scavenging material embedded in an isolation structure provides improved protection of high dielectric constant (Hi-K) materials from oxygen contamination while avoiding alteration of work function and switching threshold shift in transistors including such Hi-K materials.

Method and structure to reduce FET threshold voltage shift due to oxygen diffusion

Embodiments include a method comprising depositing a hard mask layer over a first layer, the hard mask layer including; lower hard mask layer, hard mask stop layer, and upper hard mask. The hard mask layer and the first layer are patterned and a spacer deposited on the patterned sidewall. The upper hard mask layer and top portion of the spacer are removed by selective etching with respect to the hard mask stop layer, the remaining spacer material extending to a first predetermined position on the sidewall. The hard mask stop layer is removed by selective etching with respect to the lower hard mask layer and spacer. The first hard mask layer and top portion of the spacer are removed by selectively etching the lower hard mask layer and the spacer with respect to the first layer, the remaining spacer material extending to a second predetermined position on the sidewall.

Process variability tolerant hard mask for replacement metal gate finFET devices

A method of forming a semiconductor device is provided that includes forming an oxide containing isolation region in a semiconductor substrate to define an active semiconductor region. A blanket gate stack including a high-k gate dielectric layer may then be formed on the active semiconductor region. At least a portion of the blanket gate stack extends from the active semiconductor device region to the isolation region. The blanket gate stack may then be etched to provide an opening over the isolation region. The surface of the isolation region that is exposed by the opening may then be isotropically etched to form an undercut region in the isolation region that extend under the high-k gate dielectric layer. An encapsulating dielectric material may then be formed in the opening filling the undercut region. The blanket gate stack may then be patterned to form a gate structure.

Metal oxide semiconductor field effect transistor (MOSFET) gate termination

Process for enhancing strain in a channel with a stress liner, spacer, process for forming integrated circuit and integrated circuit. A first spacer composed of an first oxide and first nitride layer is applied to a gate electrode on a substrate, and a second spacer composed of a second oxide and second nitride layer is applied. Deep implanting of source and drain in the substrate occurs, and removal of the second nitride, second oxide, and first nitride layers.

Spacer and process to enhance the strain in the channel with stress liner

Silicon germanium (SiGe) is epitaxially grown on a silicon channel above nFET and pFET regions of a substrate. SiGe is removed above the nFET regions. A device includes a silicon channel above the nFET regions and a SiGe channel above the pFET regions.

CMOS SiGe channel pFET and Si channel nFET devices with minimal STI recess

A semiconductor process and apparatus includes forming &#x3c;100&#x3e; channel orientation CMOS transistors () with enhanced hole mobility in the NMOS channel region and reduced channel defectivity in the PMOS region by depositing a first tensile etch stop layer () over the PMOS and NMOS gate structures, etching the tensile etch stop layer () to form tensile sidewall spacers () on the exposed gate sidewalls, and then depositing a second hydrogen rich compressive or neutral etch stop layer () over the NMOS and PMOS gate structures () and the tensile sidewall spacers (). In other embodiments, a first hydrogen-rich etch stop layer () is deposited and etched to form sidewall spacers () on the exposed gate sidewalls, and then a second tensile etch stop layer () is deposited over the NMOS and PMOS gate structures () and the sidewall spacers ().

Method for transistor fabrication with optimized performance

An improved method for applying stress proximity technique process on a semiconductor device and the improved device is disclosed. In one embodiment, the method utilizes an additional set of sidewall spacers on one or more NFET devices during the fabrication process. This protects the one or more of the NFET devices during the activation of a compressive PFET stress liner, thereby reducing the compressive forces on the one or more NFET devices, and creating a semiconductor device with improved performance.

Method for improved fabrication of a semiconductor using a stress proximity technique process

A method of producing a metal oxide semiconductor field effect transistor (MOSFET) creates a transistor by patterning a gate structure over a substrate, forming spacers on sides of the gate structure, and forming conductor regions within the substrate on alternate sides of the gate stack. The gate structure and the conductor regions make up the transistor. In order to reduce high power plasma induced damage, the method initially applies a first plasma having a first power level to the transistor to form a first stress layer over the transistor. After the first lower-power plasma is applied, the method then applies a second plasma having a second power level to the transistor to from a second stress layer over the first stress layer. The second power level is higher (e.g., at least 5 times higher) than the first power level.

Dual layer stress liner for MOSFETS

An integrated circuit (IC) is provided that includes at least one static random access memory (SRAM) cell wherein performance of the SRAM cell is enhanced, yet with good stability and writability. In particular, the present invention provides an IC including at least one SRAM cell wherein the gamma ratio is about 1 or greater. The gamma ratio is increased with degraded pFET device performance. Morever, in the inventive IC there is no stress liner boundary present in the SRAM region and ion variation for all devices is reduced as compared to that of a conventional SRAM structure. The present invention provides an integrated circuit (IC) that comprises at least one SRAM cell including at least one nFET and at least one pFET; and a continuous relaxed stressed liner located above and adjoining the nFET and the pFET.

Structure of static random access memory with stress engineering for stability

A lateral trench in a semiconductor substrate is formed by the following steps. Form a lateral implant mask (LIM) over a top surface of the semiconductor substrate. Implant a heavy dopant concentration into the substrate through the LIM to form a lateral implant region (LIR) in the substrate. Strip the LIM exposing the top surface of the substrate. Form an epitaxial silicon layer over the top surface of the substrate burying the LIR. Form a trench mask over the epitaxial layer. Etch a trench reaching through the epitaxial layer and the LIR. Form oxidized trench sidewalls, an oxidized trench bottom and oxidized sidewalls of the LIR. Etch the oxidized sidewalls of the LIR until the LIR is exposed. Form laterally extending trenches by etching away the LIR.

Trench sidewall passivation for lateral RIE in a selective silicon-on-insulator process flow

Growing community of inventors

Schenectady, NY, United States of America

Christopher V Baiocco