International Business Machines Corporation

Globalfoundries Inc.

Christopher N Collins

Mukta G Farooq

Stefan Schmitz

Troy Lawrence Graves-Abe

Ryan Wayne Wuthrich

Michael A Cohn

Joyce C Liu

Gerd Pfeiffer

Robert J Sullivan

James Patrick Norum

Joseph P DeGeorge

Harris C Jones

Thuy L Tran-Quinn

Kurt Elmer Bastian

Italo A DiNunzio

Dominic Joseph Schepis

Chandrasekharan Kothandaraman

Herbert Lei Ho

Brian Joseph Greene

Jon Alfred Casey

Robert Hannon

Oh-Jung Kwon

Robert Anthony Rita

Claude Ortolland

Len Yuan Tsou

Jeffrey J Brown

George A Kaplita

Alan Piciacchio

Teresa L Pinto

Robert C Greenlese

Wilson Tong Lee

Leslie J Wiands

Adrienne M Tirch

James J Burte

A method of making a semiconductor device includes disposing a mask on a substrate; etching the mask to form an opening in the mask; etching a trench in the substrate beneath the opening in the mask; and implanting a dopant in an area of the substrate beneath the opening of the mask, the dopant capable of gettering mobile ions that can contaminate the substrate; wherein the dopant extends through the substrate from a sidewall of the trench and an endwall of the trench.

Implant after through-silicon via (TSV) etch to getter mobile ions

The present disclosure generally relates to semiconductor structures and, more particularly, to self-aligned nanotube structures and methods of manufacture. The structure includes at least one nanotube structure supported by a plurality of spacers and an insulator material between the spacers and contacting the at least one nanotube structure.

Self-aligned nanotube structures

The formation of TSVs (through substrate vias) for 3D applications has proven to be defect dependent upon the type of starting semiconductor substrate employed. In addition to the initial formation of TSVs via Bosch processing, backside 3D wafer processing has also shown a defect dependency on substrate type. High yield of TSV formation can be achieved by utilizing a substrate that embodies bulk micro defects (BMD) at a density between 1e4/cc (particles per cubic centimeter) and 1e7/cc and having equivalent diameter less than 55 nm (nanometers).

Electrical leakage reduction in stacked integrated circuits having through-silicon-via (TSV) structures

A trench capacitor having an increased surface area. In one embodiment, the trench capacitor is a dual trench capacitor having a first trench and a second trench wherein inner walls of the trenches electrically connect. The invention also includes a single trench capacitor wherein the trench is curved around an axis substantially perpendicular to a substrate surface.

Process of manufacturing a DRAM cell capacitor having increased trench capacitance

A cleaning wafer is used during the vaporization of particulate deposits that were previously deposited on the walls of a plasma chamber. The cleaning wafer includes a first dielectric layer, a conducting layer and a second dielectric layer covering the conducting layer.

Universal cleaning wafer for a plasma chamber

DRAM cell capacitor having increased trench capacitance

Greensheets having enhanced flexibility and strength are prepared from a greensheet casting composition comprising alumina or other ceramic having a mean particle size of less than about 1 micron and being substantially unimodal, a binder resin, a solvent system and a plasticizer. The greensheets may be formed having a thickness of about 50 microns using conventional greensheet fabricating devices. The greensheets are particularly suitable as dielectric layers for internal layer capacitors in a multilayer ceramic substrate. A preferred co-sintering heating profile to avoid blistering of the MLC package is also provided to form the capacitor containing MLC.

Process for fabricating a multilayer ceramic substrate from thin

Camber of ceramic substrates is prevented by placing a conformable load tile over substrates during sintering. The conformable load tile has an initial curvature that facilitates escape of substrate binder gases during a burn out cycle. Subsequently, the conformable load tile conforms to the substrates under the higher heat of sintering temperature to maintain flatness of the substrates. To prevent sticking of the conformable load tile to the substrates, the conformable load tile is provided with a nonstick surface.

Weighted sintering process and conformable load tile

A stacking system includes a frame having recesses therein used to partially define openings that permit gas generated during firing of a substrate within the space defined by the frame to escape without adversely affecting the substrate. A relatively thin tile placed on the frame provides the system with an additional level for substrates.

Stacking system for substrates

Growing community of inventors

Wappingers Falls, NY, United States of America

Christopher N Collins