Globalfoundries Inc.

International Business Machines Corporation

Christopher Michael Prindle

Ruilong Xie

Kwan-Yong Lim

Ajey Poovannummoottil Jacob

Xiuyu Cai

Pietro Montanini

Balasubramanian Pranatharthiharan

Soon-Cheon Seo

Min Gyu Sung

Andreas Knorr

Tek Po Rinus Lee

Tenko Yamashita

Chanro Park

Shogo Mochizuki

Julien Frougier

Andrew Mark Greene

Laertis Economikos

Sven Beyer

Jody Alan Fronheiser

Mark V Raymond

Catherine B Labelle

Linus Jang

Nigel Graeme Cave

Daniel T Pham

Emilie Bourjot

Erik P Geiss

Neeraj Tripathi

Robert Teagle

The disclosure relates to gate-all-around (GAA) transistors with a spacer support, and related methods. A GAA transistor according to embodiments of the disclosure includes: at least one semiconductor channel structure extending between a source terminal and a drain terminal; a spacer support having a first portion thereof positioned underneath and a second portion thereof positioned alongside a first portion of the at least one semiconductor channel structure; and a gate metal surrounding a second portion of the at least one semiconductor channel structure between the source and drain terminals; wherein the spacer support is positioned between the gate metal and the source or drain terminal.

Gate-all-around transistor with spacer support and methods of forming same

Embodiments of the present invention are directed to techniques for removing epitaxy defect regions (or nodules) from a semiconductor structure. In a non-limiting embodiment of the invention, a sacrificial gate is formed over a channel region of a fin. The sacrificial gate can include a gate hard mask and a spacer. A source or drain region is formed adjacent to the channel region, resulting in a defect region being formed on a surface of the gate hard mask or the spacer. An organic planarization layer (OPL) is formed on a surface of the source or drain region and the defect region is removed.

Removal of epitaxy defects in transistors

One illustrative IC product disclosed herein includes a transistor device including a gate structure positioned above an active region, first and second conductive source/drain structures positioned adjacent opposite sidewalls of the gate structure and an insulating material positioned laterally between the gate structure and each of the first and second conductive source/drain structures. The product also includes first and second air gaps positioned adjacent opposite sidewalls of the gate structure, a gate contact structure that is positioned entirely above the active region and conductively coupled to the gate structure and a source/drain contact structure that is positioned entirely above the active region and conductively coupled to at least one of the first and second conductive source/drain structures.

Gate and source/drain contact structures positioned above an active region of a transistor device

One illustrative integrated circuit product disclosed herein includes a transistor device comprising a T-shaped gate structure positioned above an active region defined in a semiconducting substrate, the T-shaped portion of the gate structure comprising a relatively wider upper portion and a relatively narrower lower portion, and first and second conductive source/drain structures positioned adjacent opposite sidewalls of the T-shaped gate structure. In this example, the product also includes first and second air gaps positioned adjacent opposite sidewall of the T-shaped gate structure, wherein each of the air gaps is positioned between at least the lower portion of one of the sidewalls of the T-shaped gate structure and the adjacent conductive source/drain structure.

Gate contact structure positioned above an active region with air gaps positioned adjacent the gate structure

One illustrative method disclosed includes, among other things, forming a gate structure around a fin and above a layer of insulating material, forming a gate spacer adjacent the gate structure and a fin spacer positioned adjacent the fin above the insulating material, the fin spacer leaving an upper surface of the fin exposed, and performing at least one etching process to remove at least a portion of the fin positioned between the fin spacer, the fin having a recessed upper surface that at least partially defines a fin recess positioned between the fin spacer. In this example, the method further includes forming an epi semiconductor material on the fin recess and removing the fin spacer from adjacent the epi semiconductor material while leaving a portion of the gate spacer in position adjacent the gate structure.

Methods of forming epi semiconductor material on a recessed fin in the source/drain regions of a FinFET device

An integrated circuit product includes a FinFET device, a device isolation region that is positioned around a perimeter of the FinFET device, and an isolation protection layer that is positioned above the device isolation region. The FinFET device includes at least one fin, a gate structure, and a sidewall spacer, the device isolation region includes a first insulating material, and the isolation protection layer includes a material that is different from the first insulating material. A first portion of the isolation protection layer is positioned under a portion of the gate structure and under a portion of the sidewall spacer, wherein a second portion of the isolation protection layer is not positioned under the gate structure and is not positioned under the sidewall spacer, the first portion of the isolation protection layer having a thickness that is greater than a thickness of the second portion.

Integrated circuit products that include FinFET devices and a protection layer formed on an isolation region

At least one method, apparatus and system disclosed herein for suppressing over-growth of epitaxial layer formed on fins of fin field effect transistor (finFET) to prevent shorts between fins of separate finFET devices. A set of fins of a first transistor is formed. The set of fins comprises a first outer fin, an inner fin, and a second outer fin. An oxide deposition process is performed for depositing an oxide material upon the set of fins. A first recess process is performed for removing a portion of oxide material. This leaves a portion of the oxide material remaining on the inside walls of the first and second outer fins. A spacer nitride deposition process is performed. A spacer nitride removal process is performed, leaving spacer nitride material at the outer walls of the first and second outer fins. A second recess process is performed for removing the oxide material from the inside walls of the first and second outer fins. An epitaxial layer deposition processed upon the set of fins. A portion of the lateral over-growth of epitaxial layer on the outer walls of the first and second outer fins is suppressed by the spacer nitride material.

Methods, apparatus and system for providing source-drain epitaxy layer with lateral over-growth suppression

One illustrative method disclosed herein includes, among other things, forming a plurality of trenches in a semiconductor substrate so as to define a plurality of fins, forming a recessed layer of insulating material comprising a first insulating material in the trenches, wherein a portion of each of the plurality of fins is exposed above an upper surface of the recessed layer of insulating material, and masking a first portion of a first fin and performing at least one first etching process to remove at least a portion of an unmasked second fin. In this example, the method further includes forming a device isolation region for the FinFET device that comprises a second insulating material and forming an isolation protection layer above the device isolation region.

Methods of forming a protection layer on an isolation region of IC products comprising FinFET devices

FinFET spacer formation includes, for example, providing an intermediate semiconductor structure having a substrate having one or more fin having a first and a second plurality of gates disposed thereon, and a first plurality of spacers disposed on sides of the first and second plurality of gates, depositing a first liner on the structure, depositing a fill material at a level along inner portions of the first liner between the gates adjacent to the one or more fin, removing outer portions of the first spacers and the first liner away from the fill material, the remaining portions of the first spacers and the first liner defining a first thickness, and depositing a second liner having a second thickness over the gates and over the remaining portions of the first spacers and the first liner, and the fill material, and wherein the first thickness is greater than the second thickness.

FinFET spacer formation on gate sidewalls, between the channel and source/drain regions

Devices and methods of fabricating integrated circuit devices for forming epi for aggressive gate pitch are provided. One method includes: obtaining an intermediate semiconductor device having a substrate, a fin structure, a plurality of stacks; etching the spacer between the plurality of stacks; growing, epitaxially, undoped silicon on a top surface of the fin structure between the plurality of stacks; depositing a liner over the undoped silicon and the plurality of stacks; etching to remove the liner and narrow the spacers, wherein the etching forms a wider portion of the spacer at the base of the stacks; etching between the plurality of stacks to remove the undoped silicon and form recesses in the fin structure; and growing, epitaxially, doped silicon between the plurality of stacks and in the fin structure. Also disclosed is an intermediate device formed by the method.

Devices and methods of forming epi for aggressive gate pitch

One illustrative method disclosed herein includes removing the sidewall spacers and a gate cap layer so as to thereby expose an upper surface and sidewalls of a sacrificial gate structure, forming an etch stop layer above source/drain regions of a device and on the sidewalls and upper surface of the sacrificial gate structure, forming a first layer of insulating material above the etch stop layer, removing the sacrificial gate structure so as to define a replacement gate cavity that is laterally defined by portions of the etch stop layer, forming a replacement gate structure in the replacement gate cavity, and forming a second gate cap layer above the replacement gate structure.

Semiconductor devices with dummy gate structures partially on isolation regions

A method of forming raised S/D regions by partial EPI growth with a partial EPI liner therebetween and the resulting device are provided. Embodiments include forming groups of fins extending above a STI layer; forming a gate over the groups of fins; forming a gate spacer on each side of the gate; forming a raised S/D region proximate to each spacer on each fin of the groups of fins, each raised S/D region having a top surface, vertical sidewalls, and an undersurface; forming a liner over and between each raised S/D region; removing the liner from the top surface of each raised S/D region and from in between a group of fins; forming an overgrowth region on the top surface of each raised S/D region; forming an ILD over and between the raised S/D regions; and forming a contact through the ILD, down to the raised S/D regions.

Raised source/drain EPI with suppressed lateral EPI overgrowth

Field-effect transistors (FETs) and methods of fabricating field-effect transistors are provided, with one or both of a source cavity or a drain cavity having different channel junction characteristics. The methods include, for instance, recessing a semiconductor material to form a cavity adjacent to a channel region of the transistor, the recessing defining a bottom channel interface surface and a sidewall channel interface surface within the cavity; providing a protective liner over the sidewall channel interface surface, with the bottom channel interface surface being exposed within the cavity; processing the bottom channel interface surface to facilitate forming a first channel junction of the transistor; and removing the protective liner from over the sidewall channel interface surface, and subsequently processing the sidewall channel interface surface to form a second channel junction of the transistor, where the first and second channel junctions have different channel junction characteristics.

Transistor(s) with different source/drain channel junction characteristics, and methods of fabrication

One method disclosed herein includes, among other things, forming sidewall spacers adjacent opposite sides of a sacrificial gate electrode of a sacrificial gate structure, forming a tensile-stressed layer of insulating material adjacent the sidewall spacers, removing the sacrificial gate structure to define a replacement gate cavity positioned between the sidewall spacers, forming a replacement gate structure in the replacement gate cavity, forming a tensile-stressed gate cap layer above the replacement gate structure and within the replacement gate cavity and, after forming the tensile-stressed gate cap layer, removing the tensile-stressed layer of insulating material.

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Poughkeepsie, NY, United States of America

Christopher Michael Prindle