Advanced Micro Devices Corporation

Globalfoundries Inc.

Christopher L Wooten

Thomas E Spikes, Jr

Tim Z Hossain

Craig William Christian

Matthew S Ryskoski

Allen Lewis Evans

Song Han

Douglas C Kimbrough

A method includes scanning a test socket after removal of a device under test to generate scan data. The scan data is compared to reference data. A presence of at least a portion of a pin in the test socket is identified based on the comparison. A test system includes a test socket, a scanner, and a control unit. The test socket is operable to receive devices under test. The scanner is operable to scan a test socket after removal of a device under test to generate scan data. The control unit is operable to compare the scan data to reference data and identify a presence of at least a portion of a pin in the test socket based on the comparison.

Method and apparatus for identifying broken pins in a test socket

In one aspect of the present invention, a method and an apparatus are provided for determining a cumulative defect measure for a wafer lot. A wafer lot is selected for inspection. At least one wafer from the lot for inspection is selected. The wafer comprises a plurality of process layers and at least some of the process layers are selected for inspection for defects. The number, type, and kill ratio of the defects on each layer of the wafer selected are determined from inspection. A cumulative defect measurement for the wafer is determined based upon the number, type, and kill ratio of the defects on all inspected layers on the wafer. The cumulative defect measurement for the wafer is extrapolated to determine a quantified indication of a defectiveness of the selected wafer lot.

Method and apparatus for measuring cumulative defects

A method for reducing die loss in a semiconductor fabrication process which employs titanium nitride and HDP oxide is provided. In the fabrication of multilevel interconnect structures, there is a propensity for defect formation in a process in which titanium nitride and HDP oxide layers are in contact along the edge of a semiconductor substrate. A dielectric interlayer is provided which improves the interfacial properties between titanium nitride and HDP oxide and thereby reduces defects caused by delamination at the titanium nitride/HDP oxide interface.

Interlayer between titanium nitride and high density plasma oxide

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Austin, TX, United States of America

Christopher L Wooten