Pdf Solutions, Incorporated

Christopher Hess

Dennis Ciplickas

Larg H Weiland

Sherry F Lee

John Kibarian

Indranil De

Kimon Michaels

Jeremy Cheng

Rakesh Vallishayee

Tomasz Brozek

Hans Eisenmann

Sheng-Che Lin

Jonathan Haigh

Stephen Lam

Andrzej Strojwas

Vyacheslav Rovner

Markus Rauscher

Carl Taylor

Nobuharu Yokoyama

Hideki Matsuhashi

Conor O'Sullivan

Kelvin Doong

Simone Comensoli

Marcin Strojwas

Timothy Fiscus

Marci Liao

Brian E Stine

David M Stashower

Joseph C Davis

Matthew Moe

Marian Mankos

Purnendu K Mozumder

Qi Hu

Balasubramanian Murugan

Michele Squicciarini

Stefano Tonello

Michele Quarantelli

Amit Joag

Richard Gene Burch

Sharad Saxena

Ratibor Radojcic

Chia-Chi Lin

Carlo Guardiani

Yuan Yu

Yih-Yuh Kelvin Doong

Meindert Martin Lunenborg

Tzupin Shen

Christoph Dolainsky

Hendrik Schneider

Jonathan O Burrows

Alberto Piadena

SiewHoon Ng

Cho-Si Huang

Abdul Mobeen Mohammed

Ben Shieh

David Goldman

Angelo Rossoni

Joe Davis

Enrico Malavasi

Abdulmobeen Mohammad

Stefano Zanella

Nicola Dragone

Michel Quarantelli

Joshi Aniruddha

Howard Read

Markus Decker

Systems, devices, and methods for performing a non-contact electrical measurement (NCEM) on a NCEM-enabled cell included in a NCEM-enabled cell vehicle may be configured to perform NCEMs while the NCEM-enabled cell vehicle is moving. The movement may be due to vibrations in the system and/or movement of a movable stage on which the NCEM-enabled cell vehicle is positioned. Position information for an electron beam column producing the electron beam performing the NCEMs and/or for the moving stage may be used to align the electron beam with targets on the NCEM-enabled cell vehicle while it is moving.

Systems, devices, and methods for performing a non-contact electrical measurement on a cell, non-contact electrical measurement cell vehicle, chip, wafer, die, or logic block

A novel system for in-product Bias Temperature Instability (BTI) characterization that allows for characterization of transistor degradation rates is disclosed; it is self-testing and can be embedded in real products without impacting the host functionality. The test data collected during product chip testing (at Electrical Wafer Sort) can be used for identification of abnormal material and for material disposition, or to predict the chip aging rate and premature failure risk due to BTI degradation. The system can also collect the data from the real time device aging in the field, during the host chip operational lifetime. The system is equipped with local programmable power supply generation and self-test capabilities to allow concurrent operations with the host application. The Devices Under Test (DUTs) consist of standard cell-based Ring Oscillators (ROs) which have the unique capability of decoupling the BTI effects on N-type and P-type MOSFET transistors. New switching circuitry is implemented that provides for minimal delay between the stress and measurement phases, thus giving the system the capability of fully characterizing the BTI relaxation dynamic.

Embedded system to characterize BTI degradation effects in MOSFETs

Methods for performing a non-contact electrical measurement on a cell, chip, wafer, die, or logic block

An IC that includes a contiguous standard cell area with a 4x3 e-beam pad that is compatible with advanced manufacturing processes and an associated e-beam testable structure.

IC with test structures and e-beam pads embedded within a contiguous standard cell area

An IC that includes a contiguous standard cell area with a 4&#xd7;3 e-beam pad that is compatible with advanced manufacturing processes and an associated e-beam testable structure.

IC with test structures and E-beam pads embedded within a contiguous standard cell area

A method for processing a semiconductor wafer uses non-contact electrical measurements indicative of at least one tip-to-side short or leakage, at least one corner short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective tip-to-side short, corner short, and via open test areas.

Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-side short or leakage, at least one corner short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective tip-to-side short, corner short, and via open test areas

An IC includes a contiguous standard cell area with first, second, and third TS-GATE-short-configured test area geometries disposed therein. In some embodiments, the contiguous standard cell area may further include: fourth and fifth TS-GATE-short-configured test area geometries, and/or other test area geometries, such as tip-to-tip-short, tip-to-side-short, diagonal-short, corner-short, interlayer-overlap-short, via-chamfer-short, merged-via-short, snake-open, stitch-open, via-open, or metal-island-open.

IC with test structures embedded within a contiguous standard cell area

An apparatus and method for testing two-terminal memory elements organized as a cross-point memory array. The apparatus allows functional testing of two-terminal memory elements organized as a cross-point memory array, and built in a short flow manufacturing process. The proposed apparatus substantially eliminates the use of any type of additional active or passive switches, selectors, or decoders. A large number of memory elements of various memory types including planar (two dimensional) or three dimensional memory structures can be tested without the need of manufacturing selectors or running the full flow process.

Passive array test structure for cross-point memory characterization

Improved processes for manufacturing wafers, chips, or dies utilize in-line data obtained from non-contact electrical measurements ('NCEM') of fill cells that contain structures configured target/expose a variety of open-circuit, short-circuit, leakage, or excessive resistance failure modes. Such processes may involve evaluating Designs of Experiments ('DOEs'), comprised of multiple NCEM-enabled fill cells, in at least two variants, all targeted to the same failure mode(s).

Process for making semiconductor dies, chips, and wafers using in-line measurements obtained from DOEs of NCEM-enabled fill cells

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Belmont, CA, United States of America

Christopher Hess