Micron Technology Incorporated

Christopher Glancey

Shams U Arifeen

Koustav Sinha

Quang Nguyen

Chan H Yoo

Xiao Li

A semiconductor package assembly includes a first mounting surface of a package substrate that faces a second mounting surface of a printed circuit board. A first structural element bond pad is mounted to the first mounting surface. A second structural element bond pad is mounted to the second mounting surface, and the first and second structural element bond pads are aligned with each other. A structural element is interconnected with a first solder joint to the first structural element bond pad and interconnected with a second solder joint to the second structural element bond pad. The structural element extends between the first and second structural element bond pads to absorb mechanical shock when a compressive force pushes one of the first and second mounting surfaces toward the other.

Methods and apparatus for using structural elements to improve drop/shock resilience in semiconductor devices

Semiconductor devices having reinforcement structures configured to mitigate thermomechanical stresses, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor package includes a semiconductor die and a substrate coupled to the semiconductor die. The substrate can include a base structure and a reinforcement structure at least partially within a die shadow region of the substrate. The reinforcement structure can be at least partially surrounded by the base structure. The reinforcement structure has a higher stiffness than the base structure.

Semiconductor devices with reinforced substrates

Semiconductor devices having interconnect structures with conductive elements configured to mitigate thermomechanical stresses, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor package includes a semiconductor die and a pillar structure coupled to the semiconductor die. The pillar structure can include a plurality of conductive elements made of a first conductive material having a first elastic modulus. The pillar structure can further include a continuous region of a second conductive material at least partially surrounding the plurality of conductive elements. The second conductive material can have a second elastic modulus less than the first elastic modulus.

Semiconductor interconnect structures with conductive elements, and associated systems and methods

Stacked semiconductor die assemblies with heat sinks and associated methods and systems are disclosed. In some embodiments, a controller carrying one or more memory dies may be attached to a front side of a substrate. The substrate may include a heat sink formed on its back side such that the heat sink can establish a thermal contact with the controller. Further, the heat sink may be coupled to a thermally conductive pad of a printed circuit board (PCB) that carries the substrate. In this manner, the controller may be provided with a heat path toward the PCB to dissipate thermal energy generated during operation. In some cases, the substrate may include a set of thermal vias extending from the heat sink toward the controller to enhance the thermal contact between the controller and the heat sink.

Stacked semiconductor die assemblies with substrate heat sinks and associated systems and methods

A microelectronic component comprises a substrate having at least one bond pad on a surface thereof and a metal pillar structure on the at least one bond pad, the metal pillar structure comprising a metal pillar on the at least one bond pad and a solder material having a portion within a reservoir within the metal pillar and another portion protruding from an end of the metal pillar opposite the at least one bond pad. Methods for forming the metal pillar structures, metal pillar structures, assemblies and systems incorporating the metal pillar structures are also disclosed.

Microelectronic components including metal pillars secured to bond pads, and related methods, assemblies, and systems

A microelectronic device and/or microelectronic device package having a warpage control structure. The warpage control structure may be positioned over an encapsulating material, wherein the encapsulating material is positioned between the warpage control structure and a die positioned over a substrate. The warpage control structure may have a first thickness over a first portion of the encapsulating material and a second thickness over a second portion of the encapsulating material. Methods of forming the microelectronic device are also disclosed herein.

Warpage control in microelectronic packages, and related assemblies and methods

Various embodiments described herein provide for printed circuit boards with one or more spaces for embedding components, which can be used to implement a memory sub-system.

Circuit board with spaces for embedding components

Solder joints comprising two different solder materials having different melting points, an outer solder material extending over an inner solder material bonded to a conductive pad, the inner solder material having a lower melting point than a melting point of the outer solder material and being in a solid state at substantially ambient temperature. A metal material having a higher melting point than a melting point of either solder material may coat at least a portion of the inner solder material. Microelectronic components, assemblies and electronic systems incorporating the solder joints, as well as processes for forming and repairing the solder joints are also disclosed.

Processes for forming self-healing solder joints and repair of same, related solder joints, and microelectronic components, assemblies and electronic systems incorporating such solder joints

Methods for forming elements for microelectronic components, related conductive elements, and microelectronic components, assemblies and electronic systems incorporating such conductive elements

Growing community of inventors

Boise, ID, United States of America

Christopher Glancey